Zorro II

Zorro II is the Amiga expansion bus architecture introduced with the Commodore Amiga 2000 in 1987, derived from and backward-compatible with the side expansion connectors of the A1000 and A500. It presents an 86-pin dual-row edge connector (43 fingers per side, 0.1" centre spacing, compatible with AMP 2-530841-1) carrying a buffered version of the Motorola 68000 processor bus: a 24-bit address bus (A23–A1), a 16-bit data bus (D15–D0), and all primary 68000 control signals, running at the Amiga system clock of approximately 7.16 MHz. The A2000 also provides seven internal 100-pin Zorro II slots for plug-in cards, but the 86-pin connector documented here is the external side expansion port shared across the A500, A1000, A2000, and A2000B. AutoConfig (CONFIGIN*/CONFIGOUT* daisy-chain) allows expansion cards to self-identify and be automatically mapped into the Amiga address space during boot. The power supply available at the 86-pin connector is sufficient only for ROM cartridges; cards requiring significant current must draw power via the internal 100-pin slots.

Notes

• The connector is a standard dual-row edge connector, 43 fingers per side, 0.1" (2.54 mm) centre spacing. Compatible connector types include AMP 2-530841-1 (solder tail), AMP 4-530396-7 (wire wrap), and AMP 1-530826-2 (card extender).
• The 7M clock is not directly available at the 86-pin connector; it can be derived externally as C3* XNOR C1*.
• Columns A500, A1000, A2000, and A2000B indicate which machines carry each signal on this connector. An X marks the signal as present; blank indicates it is absent or not connected on that variant.
• The A2000B revision added the /BOSS signal (pin 20) to allow a second processor card to take control of the bus.
• Power supply from this connector is limited; cards that require more than ROM-cartridge levels of current must use the internal 100-pin Zorro II slots.
• All signal lines are 5V TTL-compatible logic levels.

Signals

• GND — Ground reference (pins 1–4, 13, 25, 37, 49, 61, 73, 85).
• +5V — +5 V DC power supply (pins 5–6).
• -5V — −5 V DC power supply (pin 8).
• +12V — +12 V DC power supply (pin 10).
• 28CLOCK — 28 MHz clock, present on A2000/A2000B only (pin 9).
• /COPCFG — Configuration Output; daisy-chained AutoConfig signal, A2000/A2000B only (pin 11).
• CONFIG IN, Grounded — AutoConfig chain input; held low (grounded) to initiate the configuration sequence (pin 12).
• /C3 — Phase-shifted colour clock signal (pin 14).
• CDAC — Colour DAC clock; used for display timing (pin 15).
• /C1 — Colour clock signal, complement of C3 (pin 16).
• /OVR — Override; asserted by an expansion card to suppress internal chip selects and take over the addressed memory region (pin 17).
• RDY — Ready; indicates that the expansion bus is ready for a bus cycle (pin 18).
• /INT2 — Interrupt level 2 request, open-collector (pin 19).
• /PALOPE — PAL output enable, present on A500/A1000 only (pin 20); absent on stock A2000; replaced by /BOSS on A2000B.
• /BOSS — Asserted by a processor accelerator card to indicate it has taken over as bus master; A2000B only (pin 20).
• A1–A23 — 68000 address bus, 24-bit (pins 29, 27, 26, 24, 23, 21, 28, 30, 32, 34, 36, 38, 39, 41, 43, 45, 47, 52, 54, 56, 58, 57, 59).
• /INT6 — Interrupt level 6 request, open-collector (pin 22).
• FC0–FC2 — 68000 function code outputs indicating processor state (supervisor/user, data/program) (pins 31, 33, 35).
• /IPL0–/IPL2 — Interrupt priority level inputs to the 68000 (pins 40, 42, 44).
• /BEER — Bus Error; asserted to terminate a bus cycle with an error condition (pin 46).
• /VPA — Valid Peripheral Address; used for 6800-compatible peripheral timing (pin 48).
• ECLK — E Clock; 68000-derived enable clock for 6800-family peripherals, approximately 716 kHz (pin 50).
• /VMA — Valid Memory Address; 6800-bus handshake signal (pin 51).
• RST — System reset (pin 53).
• /HLT — Halt; asserted by the 68000 to indicate a double bus fault or externally to halt the processor (pin 55).
• /BR — Bus Request; used on A500/A1000 to request the bus from the 68000 (pin 60).
• /CBR — Chip Bus Request; A2000/A2000B variant of the bus request signal (pin 60).
• /BGACK — Bus Grant Acknowledge; asserted by the requesting device once it has taken control of the bus (pin 62).
• /BG — Bus Grant; asserted by the 68000 in response to /BR (A500/A1000) (pin 64).
• /CBG — Chip Bus Grant; A2000/A2000B equivalent of /BG (pin 64).
• D0–D15 — 68000 data bus, 16-bit (pins 75, 77, 79, 81, 83, 86, 84, 82, 80, 78, 76, 65, 67, 69, 71, 63).
• /DTACK — Data Transfer Acknowledge; asserted by the target to complete a bus cycle (pin 66).
• R/W — Read/Write direction line; high = read, low = write (pin 68).
• /LDS — Lower Data Strobe; qualifies the low byte (D7–D0) of the data bus (pin 70).
• /UDS — Upper Data Strobe; qualifies the high byte (D15–D8) of the data bus (pin 72).
• /AS — Address Strobe; asserted when a valid address is present on the address bus (pin 74).

References

• Amiga Hardware Reference Manual, 3rd Edition (Commodore-Amiga Inc., 1991)
• Commodore Amiga A500/A2000 Technical Reference Manual (Commodore, 1987)
• The Zorro III Bus Specification (Dave Haynie, Commodore Systems Engineering)
• Amiga Hardware Reference Manual, 2nd Edition (Commodore-Amiga Inc., 1989)

Category:Buses Connectors