Apple IIe I/O Slot

Apple II - 50 pin female bus connector

The Apple IIe provides seven peripheral expansion slots (Slots 1–7), each using a 50-pin double-sided edge connector with 25 contacts per side, spaced at 100 mil (0.1 in) pitch with 200 mil row spacing. Introduced in 1977 on the original Apple II, the slot architecture remained consistent across the Apple II, II+, IIe, and IIGS, giving peripheral cards direct access to the 6502-family address and data buses. Power rails on each slot supply +5 V, −5 V, +12 V, and −12 V, with current budgets defined per slot in the Apple IIe Technical Reference Manual (1985). Slot 7 carries additional signals — SYNC and 3.58M — used for composite video timing.

Notes

• Connector type: double-sided PCB edge connector, 25 contacts per side, 100 mil pitch, 200 mil row spacing.
• All seven slots carry identical bus signals except Slot 7, which additionally provides SYNC (horizontal/vertical sync) and 3.58M (colour burst reference) for video peripheral cards.
• Power budgets per slot: +5 V at 500 mA, −5 V at 200 mA, +12 V at 250 mA, −12 V at 200 mA (Apple IIe Technical Reference Manual, Chapter 7).
• DMA IN/OUT and INT IN/OUT form daisy-chain interrupt and DMA priority chains across the seven slots; Slot 7 is highest priority, Slot 1 lowest.
• Active-low signals are prefixed with / (e.g. /NMI, /IRQ, /RES, /INH, /DMA, /DEVSEL, /STROBE).
• The Apple IIe also provides a separate 60-pin auxiliary (I/O) slot distinct from these seven peripheral slots; that connector carries the video data bus (VID0–VID7), memory data bus (MD0–MD7), RAM address lines (RA0–RA10), and 80-column control signals, primarily for the 80-column text card.

Signals

• GND — Ground reference.
• DMA IN — DMA daisy-chain input; asserted by a higher-priority slot holding the bus.
• INT IN — Interrupt daisy-chain input from a higher-priority slot.
• /NMI — Non-maskable interrupt; triggers the 6502 NMI vector.
• /IRQ — Maskable interrupt request to the 6502.
• /RES — System reset; resets the 6502 and peripheral cards.
• /INH — Inhibit; peripheral card asserts this to disable on-board ROM/RAM at that address range.
• -12V — −12 V power rail.
• -5V — −5 V power rail.
• NC — No connection.
• 7M — 7.159 MHz clock (twice the CPU clock), derived from the master oscillator; useful for generating baud rates and video timing.
• Q3 — Phase 3 of the system clock; high during the first half of PHI0 high, used by memory timing circuits.
• CLK1 (PHI1) — Phase 1 clock output from the 6502; inverse of CLK0/PHI0.
• USER 1 — User-defined signal; purpose varies by peripheral card design.
• CLK0 (PHI0) — Phase 0 (system clock) output; approximately 1 MHz; output from the slot to peripheral cards.
• /DEVSEL — Device select; asserted low by the system when the slot’s I/O address space ($C0n0–$C0nF, where n = slot number) is being accessed.
• D0–D7 — 8-bit bidirectional data bus shared with the 6502.
• +12V — +12 V power rail.
• +5V — +5 V power rail (logic supply).
• DMA OUT — DMA daisy-chain output to the next lower-priority slot.
• INT OUT — Interrupt daisy-chain output to the next lower-priority slot.
• /DMA — Direct memory access request; peripheral asserts this to take control of the address and data buses.
• RDY — Ready; pulled low by a peripheral to insert wait states into 6502 bus cycles.
• /STROBE — I/O strobe; asserted when any slot’s device-select space ($C800–$CFFF) is accessed, used for extended ROM on peripheral cards.
• R/W — Read/Write signal from the 6502; high = read, low = write.
• A0–A15 — 16-bit address bus from the 6502; bidirectional to allow DMA masters to drive addresses.
• I/O SEL — I/O select; asserted when the slot’s ROM space ($Cn00–$CnFF, where n = slot number) is accessed, enabling the card’s on-board firmware.

References

• Apple IIe Technical Reference Manual — Apple Computer, Inc. / Addison-Wesley, 1985
• Apple IIe Auxiliary Slot Pinout (schematic) — Apple Computer, Inc. (archived)

Category:Buses Connectors