PCI Express 8x

PCI Express x8 card-edge connector pinout: 98 pins (49 per side A/B) at 1.0 mm pitch, carrying eight serial differential lanes plus power and management signals.

PCI Express 1x - 98 pin Female Connector PCI Express 1x - 98 pin Female Connector

The PCI Express (PCIe) x8 connector is a card-edge slot defined by the PCI Special Interest Group (PCI-SIG) in the PCI Express Card Electromechanical (CEM) Specification, with Revision 3.0 published in July 2013. It carries eight serial point-to-point differential lanes (each lane a transmit and a receive differential pair) replacing the shared parallel bus of conventional PCI, and provides +12 V and +3.3 V power rails alongside management signals such as SMBus, JTAG, and presence-detect lines. The connector uses a 1.0 mm contact pitch and totals 98 pins (49 per side A and B), supporting link speeds of 2.5 GT/s (Gen 1), 5.0 GT/s (Gen 2), and 8.0 GT/s (Gen 3) on the same physical slot. PCIe x8 slots are widely used in servers and workstations for network interface cards, storage controllers (HBAs), and GPU-compute cards, and are backward compatible — an x4 card inserted in an x8 slot negotiates to x4 speed.

PinSide B ConnectorSide A Connector
#NameDescription
1+12v+12 volt power
2+12v+12 volt power
3RSVDReserved
4GNDGround
5SMCLKSMBus clock
6SMDATSMBus data
7GNDGround
8+3.3v+3.3 volt power
9JTAG1+TRST#
103.3Vaux3.3v volt power
11WAKE#Link Reactivation
12RSVDReserved
13GNDGround
14HSOp(0)Transmitter Lane 0, Differential pair
15HSOn(0)GND
16GNDGround
17PRSNT#2Hotplug detect
18GNDGround
19HSOp(1)Transmitter Lane 1, Differential pair
20HSOn(1)GND
21GNDGround
22GNDGround
23HSOp(2)Transmitter Lane 2, Differential pair
24HSOn(2)GND
25GNDGround
26GNDGround
27HSOp(3)Transmitter Lane 3, Differential pair
28HSOn(0)GND
29GNDGround
30RSVDReserved
31PRSNT#2Hot plug detect
32GNDGround
33HSOp(4)Transmitter Lane 4, Differential pair
34HSOn(4)GND
35GNDGround
36GNDGround
37HSOp(5)Transmitter Lane 5, Differential pair
38HSOn(5)GND
39GNDGround
40GNDGround
41HSOp(6)Transmitter Lane 6, Differential pair
42HSOn(6)GND
43GNDGround
44GNDGround
45HSOp(7)Transmitter Lane 7, Differential pair
46HSOn(7)GND
47GNDGround
48PRSNT#2Hot plug detect
49GNDGround

Notes

  • The x8 slot is physically longer than x4 but shorter than x16; an open-ended x8 slot may accept x16 cards electrically limited to x8 speed.
  • Contact pitch is 1.0 mm; sides A and B are on opposite faces of the card edge.
  • The keying notch separates the power/management section (pins 1–11) from the high-speed lane section (pins 12–49 on each side).
  • PRSNT1# and PRSNT2# are presence-detect signals used by the system to detect card insertion and enable hot-plug support.
  • PERST# (not shown in this table) is the PCIe reset signal driven by the system to the add-in card.
  • All TX and RX high-speed pairs must be AC-coupled per the PCIe Base Specification; coupling capacitors are placed on the add-in card.
  • Gen 1 (2.5 GT/s), Gen 2 (5.0 GT/s), and Gen 3 (8.0 GT/s) use the same connector and are negotiated at link training time.

Signals

  • +12V — primary power rail supplying the add-in card
  • 3.3Vaux — auxiliary 3.3 V rail, always present even when main power is off; used to maintain wake logic
  • +3.3V — secondary power rail
  • GND — signal and power ground
  • SMCLK — SMBus clock line for system-management communication
  • SMDAT — SMBus data line for system-management communication
  • WAKE# — active-low signal asserted by the card to request link reactivation from a low-power state
  • JTAG1 (+TRST#) — JTAG Test Reset, part of the boundary-scan chain for board-level testing
  • RSVD — reserved; must not be connected by the add-in card
  • PRSNT#2 — presence-detect output from the card; pulled low to indicate card is seated; also used for hot-plug detection
  • HSOp(n) / HSOn(n) — high-speed output (transmitter) differential pair for lane n; positive (+) and negative (−) signals of the serial lane

References

Category:Buses Connectors