AGP Bus

AGP (Accelerated Graphics Port) slot connector: 66-pin-per-side pinout, voltage keying, 1x–8x speed grades and AGP-specific signals.

AGP = Accelerated Graphics Port

Accelerated Graphics Port (AGP) provides a dedicated high-speed path between the PC’s graphics controller and system memory, letting the controller read texture maps directly from system memory instead of caching them in limited local video memory. Developed by Intel and first specified in 1996 (AGP 1.0), it is derived from PCI but operates as an independent point-to-point port reserved for a single graphics card. AGP was the mainstream graphics interface from 1997 until the mid-2000s, when it was superseded by PCI Express. Successive revisions raised the transfer rate from 266 MB/s (1x) through 533 MB/s (2x) and 1066 MB/s (4x) to 2133 MB/s (8x).

AGP advantages

  • Texture maps of unlimited size, detail, and realism can be employed.
  • 3D applications will also run faster when the need to pre-fetch and cache textures in local video memory is eliminated. How much faster? Up to 12.6 times more frames per second.
  • By minimizing the need for video memory, AGP helps OEMs control the costs of new PC designs.
  • Video traffic will fly seamlessly across the AGP bus to the user’s screen.
  • Systems will have more stability when bandwidth-intensive graphics and video traffic is removed from the PCI bus.

AGP Bus – 132-pin connector

PinSignal NamePinSignal Name
A1+12 V dcB1spare
A2spareB2+5 V dc
A3Reserved *B3+5 V dc
A4USB-B4USB+
A5GroundB5Ground
A6INTA#B6INTB#
A7RST#B7CLK
A8GNT#B8REQ#
A9VCC 3.3B9VCC 3.3
A10ST1B10ST0
A11ReservedB11ST2
A12PIPE#B12RBF#
A13GroundB13Ground
A14SpareB14Spare
A15SBA1B15SBA0
A16VCC 3.3B16VCC 3.3
A17SBA3B17SBA2
A18ReservedB18SB_STB
A19GroundB19Ground
A20SBA5B20SBA4
A21SBA7B21SBA6
A22KeyB22Key
A23KeyB23Key
A24KeyB24Key
A25KeyB25Key
A26AD30B26AD31
A27AD28B27AD29
A28VCC 3.3B28VCC 3.3
A29AD26B29AD27
A30AD24B30AD25
A31GroundB31Ground
A32ReservedB32AD STB1
A33C/BE3#B33AD23
A34Vddq 3.3B34Vddq 3.3
A35AD22B35AD21
A36AD20B36AD19
A37GroundB37Ground
A38AD18B38AD17
A39AD16B39C/BE2#
A40Vddq 3.3B40Vddq 3.3
A41FRAME#B41IRDY#
A42SpareB42Spare
A43GroundB43Ground
A44SpareB44Spare
A45VCC 3.3B45VCC 3.3
A46TRDY#B46DEVSEL#
A47STOP#B47Vddq 3.3
A48SpareB48PERR#
A49GroundB49Ground
A50PARB50SERR#
A51AD15B51C/BE1#
A52Vddq 3.3B52Vddq 3.3
A53AD13B53AD14
A54AD11B54AD12
A55GroundB55Ground
A56AD9B56AD10
A57C/BE0#B57AD8
A58Vddq 3.3B58Vddq 3.3
A59ReservedB59AD STB0
A60AD6B60AD7
A61GroundB61Ground
A62AD4B62AD5
A63AD2B63AD3
A64Vddq 3.3B64Vddq 3.3
A65AD0B65AD1
A66SMB1B66SMB0
  • This reserved pin should be connected to Ground

Notes

  • Voltage keying. AGP cards and slots are keyed by signalling voltage so a card cannot be inserted into an incompatible slot: 3.3 V (AGP 1.0, 1x/2x), 1.5 V (AGP 2.0, 4x) and 0.8 V signalling (AGP 3.0, 8x). A Universal card carries both notches and fits either a 3.3 V or a 1.5 V slot; the card declares its voltage to the chipset on the TYPEDET# pin (open = 3.3 V, grounded = 1.5 V).
  • Speed grades. 1x = 266 MB/s, 2x = 533 MB/s, 4x = 1066 MB/s and 8x = 2133 MB/s; the faster grades use source-synchronous strobes (AD_STB, SB_STB) to clock several transfers per cycle.
  • Point-to-point. Unlike the shared PCI bus, AGP connects a single graphics card to the chipset, which relaxes the timing budget and permits higher clock rates. It is not hot-pluggable, and the card seats at right angles to the board.
  • IDSEL. The connector has no IDSEL pin; the card ties AD16 to its IDSEL input for PCI-style configuration.
  • AGP Pro. A longer AGP Pro connector adds power contacts for high-end workstation cards; a standard AGP card fits an AGP Pro slot, but not the reverse.

Signals

  • PIPE# — Pipelined request; the master enqueues full-width requests on the AD bus (an alternative to sideband addressing).
  • SBA[7:0] — Sideband Address port carrying address and command from the card to the chipset.
  • ST[2:0] — Status from the chipset’s arbiter (qualified by GNT#) telling the card what to do next.
  • RBF# — Read Buffer Full; the card signals that it cannot currently accept low-priority read data.
  • AD_STB0 / AD_STB1 — source-synchronous strobes timing AD[15:0] and AD[31:16] for 2x and faster transfers.
  • SB_STB — strobe timing the sideband address bus.
  • AD[31:0] / C/BE[3:0]# — multiplexed address/data and command/byte-enable lines, as on PCI.
  • REQ# / GNT# — bus request and grant; GNT# also carries the ST[2:0] status.
  • USB+ / USB- — optional USB pair routed through the connector on some boards.
  • SMB0 / SMB1 — System Management Bus clock and data.

References

Category:Buses Connectors