Apple Macintosh Processor-Direct Slot (PDS)

Apple Macintosh - Euro-DIN 120-pin socket Processor-Direct Slot

The Macintosh Processor-Direct Slot (PDS) is a proprietary Apple expansion interface that provides direct access to the CPU’s address, data, and control lines — bypassing the NuBus arbitration layer and offering lower latency than a standard NuBus slot. The PDS exists in two electrically incompatible variants: a 96-pin Euro-DIN connector used in the Macintosh SE and Macintosh Portable, and a 120-pin Euro-DIN connector used in the SE/30 and the Macintosh II family (IIci, IIfx, and IIsi). The 120-pin variant exposes the full 68030 bus including 32-bit addressing, function codes, cache control, and dynamic bus sizing signals. Because the slot is model-specific and directly tied to the CPU, expansion cards are generally not interchangeable between machine models without an adaptor; the IIsi, for example, requires an adaptor kit to accept SE/30 PDS cards, and the card must also support the IIsi’s 20 MHz clock speed.

Table with differences found in the Apple Macintosh IIfx computers

Notes

• The connector is a 120-pin Euro-DIN (IEC 60603-2) type, arranged in three rows (A, B, C) of 40 pins each.
• This pinout describes the 68030 PDS as used in the Macintosh SE/30 and Macintosh II family; it is electrically and mechanically incompatible with the 96-pin 68000 PDS found in the Macintosh SE and Macintosh Portable.
• Signal names prefixed with / are active-low; signals suffixed with * are documented as directly connected to the 68030 CPU pins with minimal buffering.
• The IIfx difference table lists pin reassignments specific to the Macintosh IIfx; only pins that differ from the standard 68030 PDS pinout are shown. The IIfx also adds proprietary bus-control signals (/PDS.MASTER, /PDS.BG, /PDS.BR, /SLOT.E) to support its unusual multi-processor bus architecture.
• B39 /SLOT.E on the IIfx is used for address-map slot replacement, allowing a PDS card to occupy the slot E address range normally used by NuBus.
• Power rails available: +5 V (multiple pins), −5 V (B40), +12 V (C40), −12 V (A40), and Ground. Cards should not exceed the logic board’s current budget for each rail.
• Cards designed for the SE/30 can operate in the IIsi via an Apple-supplied adaptor kit, provided the card supports the IIsi’s 20 MHz bus clock and uses 32-bit rather than 24-bit addressing.

Signals

• A0–A31 — 68030 32-bit address bus; all 32 lines are exposed, enabling full 32-bit addressing mode required by System 7 and later.
• D0–D31 — 68030 32-bit data bus, distributed non-sequentially across rows A, B, and C.
• /AS* — Address Strobe; asserted by the CPU to indicate a valid address on the bus.
• /DS* — Data Strobe; asserted to indicate that valid data is present or being accepted.
• R/W* — Read/Write; high for a read cycle, low for a write cycle.
• /DSACK0*, /DSACK1* — Data Transfer and Size Acknowledge; two-bit handshake from a peripheral indicating transfer completion and bus port size (8-bit, 16-bit, or 32-bit).
• /STERM* — Synchronous Cycle Termination; allows fast peripherals to terminate a bus cycle in a single clock.
• SIZ0, SIZ1 — Transfer Size; encodes the number of bytes the CPU intends to transfer in the current bus cycle.
• FC0, FC1, FC2 — Function Codes; indicate the processor state (user/supervisor) and address space (data/program) of the current bus cycle.
• /IPL0*, /IPL1*, /IPL2* — Interrupt Priority Level; three-line encoded input to the 68030 indicating the highest pending interrupt level (0–7).
• /IRQ1, /IRQ2, /IRQ3 — System interrupt request lines from the VIA/interrupt controller; available on the PDS for cards that need to assert interrupts.
• /BR* — Bus Request; asserted by the PDS card to request ownership of the local bus from the CPU.
• /BG* — Bus Grant; asserted by the CPU in response to /BR*, granting bus mastership.
• /BGACK* — Bus Grant Acknowledge; asserted by the requesting device once it has taken control of the bus.
• /BUSLOCK — Bus Lock; holds the bus locked across indivisible read-modify-write cycles.
• /RESET* — System Reset; bidirectional; a PDS card may drive this line to assert a hardware reset.
• /HALT* — Halt; bidirectional; causes the 68030 to suspend bus activity after the current bus cycle.
• /BERR* — Bus Error; asserted to signal that the current bus cycle has terminated abnormally.
• /CIOUT* — Cache Inhibit Out; driven by the CPU to indicate that the current bus cycle should not be cached.
• /CBREQ* — Cache Burst Request; indicates the CPU wishes to perform a burst cache fill.
• /CBACK* — Cache Burst Acknowledge; returned by the memory subsystem to continue a burst cycle.
• /RMC* — Read-Modify-Cycle; asserted during an indivisible read-modify-write (TAS or CAS) cycle.
• CPUCLOCK — CPU bus clock (nominally 16 MHz on the SE/30, 20 MHz on the IIsi/IIfx); the primary timing reference for PDS cards.
• C16M — 16 MHz reference clock; present even on machines with a faster CPU clock.
• ECLK — E-Clock; a 1/10-frequency derivative of the CPU clock, compatible with older 6800-family peripheral timing (purpose marked ? in the original table; this is a standard 68030 signal).
• /TM0A, /TM1A — Transfer Modifier signals on the 68030 bus; used in conjunction with function codes to further qualify bus cycle type (purpose marked ? in the original table).
• PWROFF (C1) — Connected to the system power-control logic; asserting this line can initiate a soft power-off sequence on supported models.
• /NUBUS (C2) — Logic board signal that signals to the PDS slot whether the board is configured in NuBus mode (purpose marked ? in the original table; specific behaviour is model-dependent).
• ECS (IIfx B1) — Early Cycle Start; an IIfx-specific signal asserted one clock before /AS* to give high-speed peripherals extra setup time.
• /PDS.MASTER (IIfx A2) — IIfx PDS bus master request/grant signal (purpose marked ?; part of the IIfx multi-processor bus arbitration scheme).
• /PDS.BG (IIfx B3) — IIfx PDS Bus Grant (purpose marked ?; companion to /PDS.MASTER in the IIfx arbitration logic).
• /IRQ15 (IIfx B4), /IRQ6 (IIfx C4) — Additional interrupt lines present on the IIfx PDS (specific source assignments marked ?; values are IIfx-specific interrupt controller outputs).
• /PFW (IIfx C1) — Power Fail Warning / Shutdown Bit; IIfx variant of the power-control signal at C1 of the standard pinout.
• /PDS.BR (IIfx C3) — IIfx PDS Bus Request; part of the IIfx-specific multi-master arbitration (purpose marked ? in original table).
• /SLOT.E (IIfx B39) — Slot E address-space replace signal on the IIfx; allows a PDS card to appear in the NuBus slot E address range.

References

• Guide to the Macintosh Family Hardware, Second Edition — Apple Computer, Inc. / Addison-Wesley, 1990. Chapter 14 documents both the 96-pin 68000 PDS and the 120-pin 68030 PDS signal tables (Tables 14-1, 14-3, 14-5, 14-6, 14-7).

Category:Buses Connectors