EISA

EISA = Extended Industry Standard Architecture

EISA (Extended Industry Standard Architecture) is a 32-bit PC expansion bus announced in September 1988 by the “Gang of Nine” consortium — Compaq, AST, Epson, HP, NEC, Olivetti, Tandy, Wyse, and Zenith — as an open alternative to IBM’s proprietary MCA bus. It extends the 16-bit ISA (AT) bus to 32-bit data and address widths whilst retaining full backward compatibility with existing 8-bit XT and 16-bit AT cards. The bus clock (BCLK) runs at a maximum of 8.33 MHz, yielding a peak transfer rate of approximately 33 MB/s in 32-bit burst mode; a separate OSC pin supplies a fixed 14.318 MHz reference. EISA enjoyed widespread use in servers and high-end workstations throughout the early 1990s before being superseded by PCI.

EISA connectors carry two levels of contacts. The upper level holds the ISA-compatible signals — rows A/B for the ISA 8-bit segment and C/D for the ISA 16-bit segment — so that a plain ISA card seats on the upper contacts only. A deeper, lower level adds the EISA-only signals on rows E/F and G/H, reached by the longer fingers of an EISA card. Rows A, C, E and G are on the component side of the card; rows B, D, F and H are on the solder side.

62+38 PIN EDGE CONNECTOR at the computer.

Notes

The EISA slot uses a distinctive two-level PCB edge connector totalling 198 pins. The upper rows (A/B and C/D) replicate the 98-pin ISA layout and accept standard ISA cards; the lower inlay rows (E/F and G/H) carry the EISA-specific 32-bit extension signals and are recessed below a keying ridge that prevents ISA cards from making contact with them. This physical keying means ISA cards seat only in the upper contacts and operate normally, while EISA cards engage both levels. Supply voltages defined in the specification are +5 V, −5 V, +12 V, and −12 V; in practice, −5 V was frequently omitted by motherboard manufacturers from the early 1990s onwards. The slot is mechanically incompatible with IBM MCA cards.

Signals

• +5, -5, +12, -12: Power supplies. −5 V is often not implemented on production boards.
• AEN: Address Enable. Asserted when a DMAC has control of the bus, preventing I/O devices from responding to command lines during a DMA transfer.
• BALE: Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. Memory devices should latch the LA bus on the falling edge of BALE.
• BCLK: Bus Clock, 33% duty cycle. Maximum 8.33 MHz as specified; some systems permit 10 MHz.
• BE(x): Byte Enable. Indicates which bytes on the 32-bit data bus contain valid data during the current transfer.
• CHCHK: Channel Check. A low signal generates an NMI. Bit 7 of port 70h (NMI enable) and bit 3 of port 61h (channel-check recognition) must both be zero for the NMI to reach the CPU.
• CHRDY: Channel Ready. Held low by a slow slave device to insert wait states; the slave raises it high when ready to complete the bus cycle. Should not be used simultaneously with NOWS.
• CMD#: Command Phase. Indicates that the bus cycle is in the command (data-transfer) phase. Remains asserted from the falling edge of START# until the end of the cycle.
• SD0–SD16: System Data lines; bidirectional and tri-state. (ISA-compatible portion of the data bus.)
• DAKx: DMA Acknowledge for channel x.
• DRQx: DMA Request for channel x.
• EX16#: EISA Slave Size 16. Driven by the slave device to indicate that it supports 16-bit transfers.
• EX32#: EISA Slave Size 32. Driven by the slave device to indicate that it supports 32-bit transfers.
• EXRDY: EISA Ready. When asserted high the current cycle ends on the next rising edge of BCLK; the slave drives it low to insert wait states.
• IO16#: I/O Size 16. Generated by a 16-bit slave when addressed by a bus master.
• IORC#: I/O Read Command.
• IOWC#: I/O Write Command.
• IRQx: Interrupt Request lines. IRQ2 carries the highest priority in the cascaded 8259 arrangement.
• LAxx: Latchable Address lines (LA2–LA31), providing the 32-bit EISA address extension for up to 4 GB of addressing.
• LOCK#: Asserting this signal prevents other bus masters from requesting control of the bus during an indivisible read-modify-write sequence.
• MAKx: Master Acknowledge for slot x. Signals that the bus-master request on MREQx has been granted by the arbiter.
• MASTER16#: 16-bit Bus Master. Generated by an ISA bus master when initiating a bus cycle.
• M/IO#: Memory or Input-Output. Distinguishes memory cycles from I/O cycles on the current bus transaction.
• M16#: Memory Access, 16-bit.
• MRDC#: Memory Read Command.
• MREQx: Master Request for slot x. Slot-specific signal by which an add-in card requests ownership of the bus.
• MSBURST#: Master Burst. Asserted by the bus master in response to SLBURST# to confirm that burst transfers are supported.
• MWTC#: Memory Write Command.
• NOWS#: No Wait State. Shortens the bus cycle by suppressing default wait states from the ready timer. Should not be asserted simultaneously with CHRDY.
• OSC: Oscillator, fixed at 14.318 MHz, 50% duty cycle. Independent of BCLK.
• REFRESH#: Asserted when the DRAM refresh logic is bus master.
• RESDRV: Reset Drive. Goes low at power-on; driving it low forces a system reset.
• SA0–SA19: System Address lines, tri-state. (ISA-compatible lower address lines.)
• SBHE#: System Bus High Enable, tri-state. Signals a 16-bit data transfer on the upper byte of the 16-bit ISA data bus.
• SLBURST#: Slave Burst. Driven by the slave to indicate that it supports burst transfers; the bus master responds with MSBURST# if it also supports bursts.
• SMRDC#: Standard Memory Read Command. Indicates a memory read within the lower 1 MB address range.
• SMWTC#: Standard Memory Write Command. Indicates a memory write within the lower 1 MB address range.
• START#: Start Phase. Asserted low at the beginning of a bus cycle; address and M/IO# are decoded during this phase before the command phase (CMD#) commences.
• TC: Terminal Count. Notifies the system that the final DMA data transfer has completed.
• W/R#: Write or Read. Distinguishes write cycles (high) from read cycles (low).

References

• EISA Specification Version 3.1 (Bitsavers)

Category:Buses Connectors