PC/104

PC/104 is a compact embedded computing standard introduced by the PC/104 Consortium in 1992, built around the ISA bus (IEEE P996) adapted for stackable modules rather than a traditional backplane and card cage. The form factor measures 3.550 × 3.775 inches (90.17 × 95.89 mm), and modules interconnect via two pin-and-socket through-hole headers — J1 (64 pins, 2×32) carrying 8-bit PC bus signals and J2 (40 pins, 2×20) adding the 16-bit AT extension signals. The name “PC/104” derives from the total pin count of 104 across both connectors. The bus clock runs at 4.77–8.33 MHz (ISA-compatible), with supply voltages of +5 V, +12 V, −5 V, and −12 V; an 8-bit module uses J1 only, whilst a full 16-bit module employs both connectors.

Notes

• J1 (64 pins, 2×32) carries the 8-bit PC bus subset; J2 (40 pins, 2×20) carries the 16-bit AT extension signals. An 8-bit module populates J1 only.
• Connectors are pin-and-socket through-hole headers rather than PCB edge-card connectors, giving PC/104 significantly greater mechanical ruggedness for embedded and industrial environments.
• Modules stack vertically at a 0.6-inch pitch without a backplane; each module passes bus signals through to the next via mating headers.
• Bus signals are electrically identical to ISA (IEEE P996); the bus clock (SYSCLK) runs at 4.77–8.33 MHz, with 8.33 MHz the specified maximum.
• Supply current limits per the specification: +5 V at 2.0 A, +12 V at 1.0 A, −5 V at 0.2 A, −12 V at 0.3 A.
• The KEY positions (pin 10 Row B on J1, and pin 19 Row C on J2) are absent (no pin) to act as polarisation keys preventing misaligned insertion.
• PC/104-Plus (1997) added a 120-pin PCI connector alongside the ISA stack; PCI-104 (2003) dropped the ISA connectors entirely when ISA was discontinued on desktop PCs.
• The PC/104 Consortium rebranded as the RMS Consortium on 16 October 2025; specification documents remain hosted at pc104.org.

Signals

J1 (8-bit PC bus signals)

• IOCHCHK* — I/O channel check; asserted low to signal a parity error on the bus
• SD0–SD7 — bidirectional 8-bit system data bus lines
• IOCHRDY — I/O channel ready; pulled low by a slow device to insert wait states
• AEN — address enable; asserted during DMA cycles to prevent I/O decoding conflicts
• SA0–SA19 — 20-bit system address bus lines (lower 20 bits)
• RESETDRV — system reset signal; drives all modules to a known state at power-on
• IRQ3–IRQ7, IRQ9 — hardware interrupt request lines (active high)
• DRQ1–DRQ3 — DMA request lines; asserted by a device to request a DMA transfer
• DACK1*, DACK2*, DACK3* — DMA acknowledge outputs from the DMA controller (active low)
• TC — terminal count; pulses high when a DMA transfer count reaches zero
• BALE — bus address latch enable; used to demultiplex addresses from the CPU
• OSC — oscillator output, nominally 14.318 MHz (colour-burst frequency reference)
• SYSCLK — system bus clock, 4.77–8.33 MHz
• SMEMR* — shorthand memory read strobe for the lower 1 MB address range (active low)
• SMEMW* — shorthand memory write strobe for the lower 1 MB address range (active low)
• IOR* — I/O read strobe (active low)
• IOW* — I/O write strobe (active low)
• REFRESH* — memory refresh cycle indicator (active low)
• ENDXFR* — end of transfer; used with bus mastering to signal transfer completion (active low)

J2 (16-bit AT extension signals)

• SBHE* — system bus high enable; indicates a transfer on the upper byte (D8–D15) of the data bus (active low)
• LA17–LA23 — latched upper address lines for addressing beyond 1 MB (not gated by AEN)
• MEMR* — memory read strobe covering the full 16 MB address range (active low)
• MEMW* — memory write strobe covering the full 16 MB address range (active low)
• SD8–SD15 — upper 8 bits of the 16-bit system data bus
• MEMCS16* — memory chip-select 16-bit; asserted by a card to indicate it supports 16-bit memory transfers (active low)
• IOCS16* — I/O chip-select 16-bit; asserted by a card to indicate it supports 16-bit I/O transfers (active low)
• IRQ10–IRQ12, IRQ14, IRQ15 — additional hardware interrupt request lines (active high)
• DACK0*, DACK5*, DACK6*, DACK7* — DMA acknowledge lines for AT-extended DMA channels (active low)
• DRQ0, DRQ5–DRQ7 — DMA request lines for AT-extended DMA channels (active high)
• MASTER* — bus master signal; asserted by an expansion card that has taken control of the bus (active low)

References

• PC/104 Specification Version 2.6 — PC/104 Embedded Consortium (now RMS Consortium)
• PC/104 Consortium History — RMS Consortium

Category:Buses Connectors