Apple II - 50 pin female
bus connector
Expansion Slot Connector for the Apple II Series Interface/Add On Cards. This Bus has been modified over the various versions of Apple IIs (check pins 19,35 and 39).
| Pin | Name | Direction | Description |
|---|---|---|---|
| 1 | /IOSEL | OUT | I/O Select. Active when page $Cn gets accessed. N.C. on slot 0 |
| 2 | A0 | IN/OUT | Buffered address bus |
| 3 | A1 | IN/OUT | Buffered address bus |
| 4 | A2 | IN/OUT | Buffered address bus |
| 5 | A3 | IN/OUT | Buffered address bus |
| 6 | A4 | IN/OUT | Buffered address bus |
| 7 | A5 | IN/OUT | Buffered address bus |
| 8 | A6 | IN/OUT | Buffered address bus |
| 9 | A7 | IN/OUT | Buffered address bus |
| 10 | A8 | IN/OUT | Buffered address bus |
| 11 | A9 | IN/OUT | Buffered address bus |
| 12 | A10 | IN/OUT | Buffered address bus |
| 13 | A11 | IN/OUT | Buffered address bus |
| 14 | A12 | IN/OUT | Buffered address bus |
| 15 | A13 | IN/OUT | Buffered address bus |
| 16 | A14 | IN/OUT | Buffered address bus |
| 17 | A15 | IN/OUT | Buffered address bus |
| 18 | R/W | IN/OUT | Buffered Read/Write signal. |
| 19 | SYNC | OUT | Only Slot 7. SYNC from Video Generator. Not on Rev 0 Boards. Testpin on Slot 1 for //e |
| 20 | /IOSTRB | OUT | I/O Strobe. Active when $C800 and $CFFF gets accessed |
| 21 | /RDY | IN | Activation during Phi1 will halt the CPU, with the address bus holding the last address |
| 22 | /DMA | IN | Activation disables the 6502"s address bus and halts the CPU |
| 23 | /INTOUT | IN | Daisy-chained interrupt output to lower priority devices |
| 24 | /DMAOUT | IN | Daisy-chained DMA output to lower priority devices |
| 25 | +5V | +5 Volt power supply. Max. 500mA for ALL peripheral boards | |
| 26 | GND | System electrical ground | |
| 27 | /DMAIN | OUT | Daisy-chained DMA input from higher priority devices |
| 28 | /INTIN | OUT | Daisy-chained interrupt input from higher priority devices |
| 29 | /NMI | IN | Non-Maskable Interrupt. Monitor ROM starts interrupt handling routine at location $3FB |
| 30 | /IRQ | IN | Interrupt ReQuest. Monitor starts the routine pointed to by $3FE/F |
| 31 | /RES | IN | RESet |
| 32 | /INH | IN | INHibits the on board ROMs ($D000-$FFFF) |
| 33 | -12V | -12 Volt power supply. Max. 200mA for ALL peripheral boards | |
| 34 | -5V | -5 Volt power supply. Max. 200mA for ALL peripheral boards | |
| 35 | COLORREF | OUT | Only Slot 7. 3.5 MHz Video COLOR REF. Not on Rev 0 Boards. Testpin on Slot 1 for //e. M2B0 on A2gs |
| 36 | 7M | OUT | 7Mhz clock |
| 37 | Q3 | OUT | 2Mhz asymetrical clock |
| 38 | PHI1 | OUT | 1 MHz phase 1 clock |
| 39 | Various | OUT | USER1 on A2: Disable adressdecode. 65C02 SYNC on A2e. M2SEL on A2gs |
| 40 | PHI0 | OUT | 1 MHz phase 0 clock (Inverted PHI1) |
| 41 | /DEVSEL | OUT | DEVice SELect. Active when $C0nX gets accessed; n - Slot#+8 |
| 42 | D7 | IN/OUT | Buffered bi-directional data bus |
| 43 | D6 | IN/OUT | Buffered bi-directional data bus |
| 44 | D5 | IN/OUT | Buffered bi-directional data bus |
| 45 | D4 | IN/OUT | Buffered bi-directional data bus |
| 46 | D3 | IN/OUT | Buffered bi-directional data bus |
| 47 | D2 | IN/OUT | Buffered bi-directional data bus |
| 48 | D1 | IN/OUT | Buffered bi-directional data bus |
| 49 | D0 | IN/OUT | Buffered bi-directional data bus |
| 50 | +12V | +12 Volt power supply. Max. 250mA for ALL peripheral boards |
- (/) Active Low Signal