Apple II - 50 pin female bus connector
The Apple II peripheral expansion slot is a proprietary 50-pin double-sided edge connector (25 contacts per side, 100 mil pitch, 200 mil row spacing) introduced with the Apple II in 1977 and retained, with minor signal changes, through the Apple IIe and Apple IIGS. It exposes the 6502-family bus directly: a 16-bit address bus (A0–A15), an 8-bit bidirectional data bus (D0–D7), phase clocks, interrupt and DMA daisy-chain lines, and four power rails (+5 V, −5 V, +12 V, −12 V). Up to seven slots are provided in the IIe (Slots 1–7); the IIGS retains the same seven slots with full backward compatibility. Several pin assignments differ between models — most notably pins 19, 35, and 39 — so card designers must account for the target platform.
| Pin | Name | Direction | Description |
|---|---|---|---|
| 1 | /IOSEL | OUT | I/O Select. Active when page $Cn gets accessed. N.C. on slot 0 |
| 2 | A0 | IN/OUT | Buffered address bus |
| 3 | A1 | IN/OUT | Buffered address bus |
| 4 | A2 | IN/OUT | Buffered address bus |
| 5 | A3 | IN/OUT | Buffered address bus |
| 6 | A4 | IN/OUT | Buffered address bus |
| 7 | A5 | IN/OUT | Buffered address bus |
| 8 | A6 | IN/OUT | Buffered address bus |
| 9 | A7 | IN/OUT | Buffered address bus |
| 10 | A8 | IN/OUT | Buffered address bus |
| 11 | A9 | IN/OUT | Buffered address bus |
| 12 | A10 | IN/OUT | Buffered address bus |
| 13 | A11 | IN/OUT | Buffered address bus |
| 14 | A12 | IN/OUT | Buffered address bus |
| 15 | A13 | IN/OUT | Buffered address bus |
| 16 | A14 | IN/OUT | Buffered address bus |
| 17 | A15 | IN/OUT | Buffered address bus |
| 18 | R/W | IN/OUT | Buffered Read/Write signal. |
| 19 | SYNC | OUT | Only Slot 7. SYNC from Video Generator. Not on Rev 0 Boards. Testpin on Slot 1 for //e |
| 20 | /IOSTRB | OUT | I/O Strobe. Active when $C800 and $CFFF gets accessed |
| 21 | /RDY | IN | Activation during Phi1 will halt the CPU, with the address bus holding the last address |
| 22 | /DMA | IN | Activation disables the 6502"s address bus and halts the CPU |
| 23 | /INTOUT | IN | Daisy-chained interrupt output to lower priority devices |
| 24 | /DMAOUT | IN | Daisy-chained DMA output to lower priority devices |
| 25 | +5V | +5 Volt power supply. Max. 500mA for ALL peripheral boards | |
| 26 | GND | System electrical ground | |
| 27 | /DMAIN | OUT | Daisy-chained DMA input from higher priority devices |
| 28 | /INTIN | OUT | Daisy-chained interrupt input from higher priority devices |
| 29 | /NMI | IN | Non-Maskable Interrupt. Monitor ROM starts interrupt handling routine at location $3FB |
| 30 | /IRQ | IN | Interrupt ReQuest. Monitor starts the routine pointed to by $3FE/F |
| 31 | /RES | IN | RESet |
| 32 | /INH | IN | INHibits the on board ROMs ($D000-$FFFF) |
| 33 | -12V | -12 Volt power supply. Max. 200mA for ALL peripheral boards | |
| 34 | -5V | -5 Volt power supply. Max. 200mA for ALL peripheral boards | |
| 35 | COLORREF | OUT | Only Slot 7. 3.5 MHz Video COLOR REF. Not on Rev 0 Boards. Testpin on Slot 1 for //e. M2B0 on A2gs |
| 36 | 7M | OUT | 7Mhz clock |
| 37 | Q3 | OUT | 2Mhz asymetrical clock |
| 38 | PHI1 | OUT | 1 MHz phase 1 clock |
| 39 | Various | OUT | USER1 on A2: Disable adressdecode. 65C02 SYNC on A2e. M2SEL on A2gs |
| 40 | PHI0 | OUT | 1 MHz phase 0 clock (Inverted PHI1) |
| 41 | /DEVSEL | OUT | DEVice SELect. Active when $C0nX gets accessed; n - Slot#+8 |
| 42 | D7 | IN/OUT | Buffered bi-directional data bus |
| 43 | D6 | IN/OUT | Buffered bi-directional data bus |
| 44 | D5 | IN/OUT | Buffered bi-directional data bus |
| 45 | D4 | IN/OUT | Buffered bi-directional data bus |
| 46 | D3 | IN/OUT | Buffered bi-directional data bus |
| 47 | D2 | IN/OUT | Buffered bi-directional data bus |
| 48 | D1 | IN/OUT | Buffered bi-directional data bus |
| 49 | D0 | IN/OUT | Buffered bi-directional data bus |
| 50 | +12V | +12 Volt power supply. Max. 250mA for ALL peripheral boards |
Notes
- Signal names prefixed with
/(or shown with a leading slash in the table) are active-low. - The slot is a 25-finger double-sided edge connector; the component side carries odd-numbered pins and the solder side carries even-numbered pins by convention.
- Power budgets are cumulative across all installed cards: +5 V is limited to 500 mA total, −5 V and −12 V to 200 mA each, and +12 V to 250 mA total for all peripheral boards.
- Slot-specific signals (pins 19, 35, 39) vary by model and by slot number:
- Pin 19 carries SYNC (horizontal/vertical video sync) only on Slot 7 of the original Apple II; on the IIe it becomes a test point on Slot 1.
- Pin 35 carries the 3.58 MHz colour-reference signal (COLORREF) on Slot 7 of the Apple II/IIe; on the IIGS it is reassigned to M2B0.
- Pin 39 is USER1 (address-decode disable) on the Apple II, 65C02 SYNC on the IIe, and M2SEL on the IIGS.
- The
/INHsignal inhibits the on-board ROMs in the $D000–$FFFF range, allowing peripheral cards to substitute their own ROM. - DMA and interrupt priority are resolved by daisy-chaining: /DMAIN/DMAOUT and /INTIN/INTOUT pass priority from higher-numbered to lower-numbered slots.
- The Apple IIGS retains the same 50-pin edge connector and maintains backward compatibility with Apple IIe peripheral cards.
Signals
- /IOSEL — I/O Select; asserted when page $Cn is accessed (where n = slot number); not connected on Slot 0.
- A0–A15 — Buffered 16-bit address bus from the 6502-family CPU.
- R/W — Buffered Read/Write signal; high = read, low = write.
- SYNC — (Slot 7 only, Apple II/II+) SYNC output from the video generator; used as a test point on Slot 1 of the IIe; absent on Revision 0 boards.
- /IOSTRB — I/O Strobe; asserted when addresses $C800–$CFFF are accessed.
- /RDY — Ready; when asserted during PHI1, halts the CPU with the address bus frozen at the last address.
- /DMA — Direct Memory Access request; disables the 6502 address bus and halts the CPU, allowing a peripheral to take bus control.
- /INTOUT — Daisy-chained interrupt output passed to lower-priority (higher-numbered) devices.
- /DMAOUT — Daisy-chained DMA output passed to lower-priority devices.
- +5V — +5 V power rail; maximum 500 mA shared across all peripheral cards.
- GND — System ground.
- /DMAIN — Daisy-chained DMA input received from higher-priority devices.
- /INTIN — Daisy-chained interrupt input received from higher-priority devices.
- /NMI — Non-Maskable Interrupt; the Monitor ROM begins interrupt handling at $3FB.
- /IRQ — Interrupt ReQuest; the Monitor begins the routine pointed to by $3FE/$3FF.
- /RES — Reset signal.
- /INH — Inhibit; disables on-board ROMs in the $D000–$FFFF range.
- −12V — −12 V power rail; maximum 200 mA shared across all peripheral cards.
- −5V — −5 V power rail; maximum 200 mA shared across all peripheral cards.
- COLORREF — (Slot 7 only, Apple II/IIe) 3.58 MHz colour reference; absent on Revision 0 boards; reassigned to M2B0 on the IIGS.
- 7M — 7 MHz master clock output.
- Q3 — 2 MHz asymmetrical clock output.
- PHI1 — 1 MHz phase-1 clock.
- Various (pin 39) — USER1 (address-decode disable) on the Apple II; 65C02 SYNC on the IIe; M2SEL on the IIGS.
- PHI0 — 1 MHz phase-0 clock (inverted PHI1).
- /DEVSEL — Device Select; asserted when $C0nX is accessed, where n = slot number + 8.
- D0–D7 — Buffered bidirectional 8-bit data bus.
- +12V — +12 V power rail; maximum 250 mA shared across all peripheral cards.
References
- Apple IIe Technical Reference Manual — Chapter 7: Hardware Implementation (Table 7-20: Expansion Slot Signals), Apple Computer, Inc. / Addison-Wesley, 1985
- Apple IIGS Hardware Reference, Apple Computer, Inc. / Addison-Wesley, 1989