VME64 - VME64x (VERSAmodule Eurocard) P1

VME64 P1 Connector - 160 pin DIN (41612, Type C Expanded) 5 rows x 32 pins [Pitch 2.54mm (.100")] @ ANSI/VITA 1-1994

VMEbus (VERSAmodule Eurocard bus) is an asynchronous parallel backplane bus architecture devised in 1980–1981 by Motorola, Mostek, and Signetics, combining the VERSAbus electrical specification with the Eurocard mechanical form factor. The P1/J1 connector shown here is the extended 160-pin variant introduced by VME64 (ANSI/VITA 1-1994) and fully elaborated by VME64x (ANSI/VITA 1.1-1997), achieving maximum theoretical bandwidths of 80 MB/s and 160 MB/s respectively. The connector is a DIN 41612 Type C Expanded (also designated IEC 60603-2), adding two outer compression rows — z and d — to the original 96-pin, 3-row DIN 41612 Type C, for a total of 5 rows × 32 pins at 2.54 mm pitch; it remains fully backward-compatible, accepting original 3-row VMEbus boards. P1/J1 carries all arbitration, control, interrupt, and the lower 16 address and 16 data lines, with the d-row providing +3.3 V power, geographical addressing, live-insertion signals, and auxiliary power rails under VME64x.

The pinouts shown below are as defined by VME64x (ANSI/VITA 1.1-1997). If you’re using the VME64 specification (ANSI/VITA 1-1994), all pins in row ’d’ become reserved, and every other non-ground pin in row ‘z’ becomes reserved; rows ’d’ and ‘z’ are not bussed in VME64. Otherwise the pinout is identical between VME64 and VME64x.

These 5-row connectors accept the original 3-row boards as a mate. The two new rows (z and d) were added as compression contacts on the exterior of the 3-row DIN 41612 Type C connector.

Notes

• (*) Active Low
• The VMEbus signal types are listed below:
  • Open collector signals which require Open Collector drivers and receivers: ACFail, BBSY, BERR, DTACK, IACK, SERDAT, SYSFAIL, SYSRESET, [IRQ1 - IRQ7], and [BR0 - BR3].
  • Three-State signals which require 3-State drivers and receivers: AS, DS0, DS1, DTACK, RETRY, IACK, LWORD, WRITE, [AM0 - AM5], [A01 - A31], and [D00 - D31].
  • Totem-Pole signals which require Totem-Pole drivers and receivers: BCLR, SYSCLK, SERCLK, IACKIN, IACKOUT, [BG0IN - BG3IN], [BG0OUT - BG3OUT].

Signal Descriptions:

• A01 - A31: Address lines [A01 - A31] carry a binary address.
• AM0 - AM5: The address modifier code [AM0 - AM5] is a “tag” that indicates the type of VMEbus cycle in progress.
• BG0IN* - BG3IN*, BG0OUT* - BG3OUT*: The bus grant signals [BG0IN* - BG3IN* and BG0OUT* - BG3OUT*] are part of the bus grant daisy chain and are driven by arbiters and requesters. The slot 01 arbiter asserts a bus grant in response to a bus request on the same level [BR0* - BR3*]. The bus grant daisy-chain starts at the slot 01 system controller and propagates from module to module until it reaches the module that initially requested the bus. Each VMEbus module has a bus grant input and a bus grant output. They are standard totem-pole class signals.
• BR0* - BR3*: Bus requests [BR0* - BR3*] are asserted by a requester whenever its master or interrupt handler needs the bus. Before accepting the bus, the master waits until the arbiter grants the bus by way of the bus grant daisy-chain [BG0IN* - BG3IN*]. They are open-collector class signals.
• D00-D31: Data bus [D00-D31] is driven by masters, slaves or interrupters. These are bi-directional signals and are used for data transfers. Different portions of the data bus are used depending upon the state of DS0*, DS1*, A01 and LWORD* pins. They are standard three-state signals. The data lines can also be used to transfer a portion of the address during MD32, MBLT and 2eVME cycles.
• DS0*, DS1*: Data strobes DS0* and DS1* are driven by masters and interrupt handlers. These signals serve not only to qualify data, but also to indicate the size and position of the data transfer. When combined with LWORD* and A01, the data strobes indicate the size and type of data transfer. DS0* - DS1* are high current three-state class signals.
• DTACK*: Data transfer acknowledge [DTACK*] is driven by slaves or interrupters. During write cycles DTACK* is asserted by a slave after it has latched data. During read and interrupt acknowledge cycles, DTACK* is asserted by a slave after data is placed onto the bus. DTACK* can be an open-collector or a high current three-state class signal.
• GA0* - GA4*: The geographical address [GA0*-GA4*] is a binary code that indicates the slot number of the backplane. They are open collector signals, and were added to the 160 pin P1/J1 connector in the VME64x specification.
• GAP*: The geographical address parity [GAP*] is tied high or floating, depending upon the parity of the geographical address lines [GA0*-GA4*]. It is an open collector signal, and was added to the 160 pin P1/J1 connector in the VME64x specification.
• GND: Ground [GND] is used both as a signal reference and a power return path.
• IACK*: Interrupt acknowledge [IACK*] is driven by interrupt handlers in response to interrupt requests. It is connected to IACKIN* at slot 01 (on the backplane), and used by the IACK* daisy-chain driver to start propagation of the [IACKIN* - IACKOUT*] daisy-chain. IACK* can be either an open-collector or a standard three-state class signal.
• IACKIN*, IACKOUT*: The interrupt acknowledge daisy chain [IACKIN* - IACKOUT*] is driven by the IACK* daisy-chain driver. These signals are used both to indicate that an interrupt acknowledge cycle is in progress, and to determine which interrupters should return a STATUS/ID. They are standard totem-pole class signals.
• IRQ1*-IRQ7*: Priority interrupt requests [IRQ1*-IRQ7*] are asserted by interrupters. Level seven is the highest priority, and level one the lowest. They are open-collector class signals.
• LI/I*: The live insertion input [LI/I*] signal is used to carry hot swap (live insertion) control information. It is a three state driven signal and was added to the 160 pin P1/J1 connector in the VME64x specification.
• LI/O*: The live insertion output [LI/O*] signal is used to carry hot swap (live insertion) control information. It is a three state driven signal and was added to the 160 pin P1/J1 connector in the VME64x specification.
• LWORD*: Long word [LWORD*] is driven by masters. It is used in conjunction with A01, DS0* and DS1* to indicate the size of the current data transfer. LWORD* is a standard three-state class signal. During 64-bit address transfers, LWORD* doubles as address bit A00. During 64-bit data transfers, LWORD* doubles as a data bit.
• MCLK, MCTL, MMD, MPR, MSD: These signals are part of the IEEE 1149.5 MTM (Module Test and Maintenance) bus. They are three-state driven signals that were added to the 160-pin P1/J1 connector in the VME64x specification (ANSI/VITA 1.1-1997).
• RESERVED: The RESERVED signal pin is obsolete and is no longer used. Under the IEEE 1014-1987 version of the bus specification there was a single reserved pin. This pin was redefined under VME64 as the RETRY* pin. The VME64x specification uses the names RsvB and RsvU for reserved pins.
• RESP*: The response [RESP*] signal is used to carry the information as defined by the 2eVME protocol. It was added to the 160 pin P1/J1 connector in the VME64x specification.
• RsvB: The reserved/bused [RsvB] signal should not be used. VME64x backplanes must bus and terminate this signal. It was added to the 160 pin P1/J1 connector in the VME64x specification.
• RsvU: The reserved/unbused [RsvU] signal should not be used. VME64x backplanes must not bus or terminate this signal. It was added to the 160 pin P1/J1 connector in the VME64x specification.
• RETRY*: [RETRY*], together with [BERR*], can be asserted by a slave to postpone a data transfer. The master must then attempt the cycle again at a later time. The retry cycle prevents deadlock (deadly embrace) conditions in bus-to-bus links and secondary buses. RETRY* is a standard three-state signal. The [RETRY*] signal was added in the ANSI/VITA 1-1994 (VME64) version of the bus specification. This pin was RESERVED in earlier versions. However, boards that support [RETRY*] should work correctly with older backplanes, as those were required to bus and terminate this signal line.
• SERA, SERB: The [SERA] and [SERB] signals are used for an (optional) serial bus such as the AUTOBAHN (IEEE 1394) or VMSbus. Under the ANSI/VITA 1-1994 (VME64) bus specification, these pins can be used for any user defined serial bus. Earlier versions of the VMEbus specification defined these pins as [SERCLK] and [SERDAT*], which were originally intended for a serial bus called VMSbus. However, they were rarely used for that purpose.
• SERCLK, SERDAT*: The [SERCLK] and [SERDAT*] signals were made obsolete under the ANSI/VITA 1-1994 (VME64) bus specification. Refer to [SERA] and [SERB] for more details.
• SYSCLK: 16 MHz utility clock [SYSCLK] is driven by the slot 01 system controller. This clock can be used for any purpose, and has no timing relationship to other VMEbus signals. SYSCLK* is a high current totem-pole class signal.
• SYSFAIL*: System fail [SYSFAIL*] can be asserted or monitored by any module. It indicates that a failure has occurred in the system. Implementation of [SYSFAIL*] is user-defined, and its use is optional. SYSFAIL* is an open-collector class signal.
• SYSRESET*: System reset [SYSRESET*] can be driven by any module and indicates that a reset (such as power-up) is in progress. SYSRESET* is an open-collector class signal.
• UsrDef, UD: Pins that are user defined [specified as “UsrDef” or “UD”] can be specified by the user. Generally, they are routed directly through the backplane so that they can be connected to cables or to rear I/O transition modules.
• VPC: Voltage pre-charge [VPC] pins form a “make first / break last” contact. They are intended to be used as pre-charge power sources for live insertion logic. These pins were added to the 160-pin P1/J1 (pins z1 and d32) and P2/J2 (pin d32) connectors in the VME64x specification. The VPC pins are connected to the +5 VDC power supply on VME64x backplanes. These pins may also be used as additional +5 VDC power pins in boards that do not support live insertion.
• +V1, -V1, +V2, -V2: The [+/- V1/V2] power pins supply 38 - 75 VDC to the bus module. They are also known as the auxiliary power pins, and were originally intended to be used as 48 VDC battery supplies in Telecom systems. However, they can be used for any purpose. These pins were added to the 160 pin P1/J1 connector in the VME64x specification.
• WRITE*: The read / write signal [WRITE*] is driven by masters. It indicates the direction of data transfer over the bus. It is asserted during a write cycle and negated during a read cycle. WRITE* is a standard three-state class signal.
• +5V STDBY: [+5V STDBY] is an optional +5 VDC standby power supply. This power pin is often connected to a rechargeable battery, eliminating the need for individual batteries on VMEbus modules. Individual batteries are often used for real-time clock and static RAM chips.
• +3.3 V: Main +3.3 VDC power source. These pins were added to the 160 pin P1/J1 connector in the VME64x specification.
• +5 VDC, +12 VDC, -12 VDC: The main system power supplies are [+5 VDC], [+12 VDC] and [-12 VDC].

References

• VMEbus Frequently Asked Questions (FAQ) — VITA (VMEbus International Trade Association)
• VITA Standards Access — ANSI/VITA 1-1994 and ANSI/VITA 1.1-1997 — VITA (VMEbus International Trade Association)
• DIN 41612 Connectors — Product Overview — HARTING Technology Group (har-bus 64 / VME64x 160-pin connector)
• Motorola / Micrology VMEbus Specification Manual, Rev C.1, October 1985 — archived at bitsavers.org via Internet Archive (original VMEbus signal definitions)

Category:Buses Connectors