Industrial PCI (IPCI)

Industrial PCI (iPCI) is a passive-backplane architecture governed by the PICMG 1.0 standard, designed to bring the conventional PCI Local Bus — as defined by the PCI Special Interest Group (PCI-SIG) — into industrial and embedded computing environments. Rather than mounting the CPU directly on a motherboard, PICMG 1.0 places the processor on a plug-in System Host Board (SHB) that connects to a passive backplane through two edge connectors, one carrying PCI signals and one carrying ISA or a custom I/O bus. The PCI section operates at 33 MHz (or optionally 66 MHz per PCI Local Bus Specification Rev 2.1 and later) with 32-bit transfers on the mandatory middle connector, plus an optional 64-bit extension, supporting 5 V and 3.3 V signalling environments. This architecture was widely used in factory automation, telecommunications, and defence systems throughout the late 1990s and 2000s; later PICMG 1.3 (SHB Express) added PCI Express lanes to the same passive-backplane concept.

The IPCI connector has three parts:

• Optional 60 pin PCI 64 bit extension (Top)
• Mandatory 120 pin PCI 32 bit (Middle)
• Optional 60 pin Custom I/O (Bottom)

UNKNOWN CONNECTOR at the backplane

UNKNOWN CONNECTOR at the device (card)

System Slot (Middle)

• 1 = Pullup resistor of 2,7 kOhm on the System Slot (CPU).
• 2 = Pullup resistor of 330 ohm on the System Slot (CPU).
• 3 = Pullup resistor of 4,7 KB ohm, if not supported by the System Slot (CPU).

Module Bus Slot (Middle)

• 1 = Pullup resistor of 2,7 kOhm on the System Slot (CPU).

Card Slot (Middle)

• 1 = Pullup resistor of 2,7 kOhm on the System Slot (CPU).

64-bit PCI (Top)

• 2 = Pullup resistor of 2,7 kOhm (5V bus system) or 8,2 kOhm (3,3V bus system) on the backplane.

ISA96/AT96 (Bottom)

VMEbus (Bottom)

ECB (Bottom)

SMP16 (Bottom)

Floppy/EIDE (Bottom)

SCSI (Bottom)

For more information see PCI Notes

Notes

• The IPCI backplane uses a 5-row (A–E), multi-column edge connector. The mandatory middle section provides 120 pins (5 rows × 24 columns × 2 sides) carrying the 32-bit PCI bus; the optional top section (60 pins) extends the bus to 64 bits; the optional bottom section (60 pins) carries a legacy or custom I/O bus (ISA/AT96, VMEbus, ECB, SMP16, Floppy/EIDE, SCSI, or other variants).
• The 32-bit PCI section supports both 5 V and 3.3 V I/O signalling environments; V(I/O) pins carry +3.3 V or +5 V depending on the board’s signalling environment.
• Bus clock is 33 MHz standard; the M66EN pin enables the optional 66 MHz mode introduced in PCI Local Bus Specification Rev 2.1 (June 1995).
• Signals marked with note 1 require a 2.7 kΩ pull-up resistor on the System Slot (SHB/CPU card); RSTIN# (note 2) requires a 330 Ω pull-up; I²C lines SLEEP#/SDAT and ICPEN#/SCLK (note 3) require a 4.7 kΩ pull-up if not already driven by the System Slot.
• 64-bit extension pins (note 2 in the top-section tables) require a 2.7 kΩ pull-up (5 V bus) or 8.2 kΩ pull-up (3.3 V bus) on the backplane.
• The three middle-section tables (System Slot, Module Bus Slot, Card Slot) share the same fundamental PCI signal assignments but differ in arbitration, clock, and initialisation-device-select (IDSEL) wiring appropriate to each slot type.
• REQ64# and ACK64# signals (B1 and C1 in the middle section) are used when the optional 64-bit extension connector is populated; their “???” annotations reflect the fact that these pins are open-collector / sustained tri-state and their behaviour depends on whether 64-bit capability is negotiated at boot.
• PAR64 (C11 in the top section) provides even parity over the upper 32 bits of the AD bus (AD[63:32]) and C/BE[7:4]# during 64-bit transfers; the “???” annotation reflects that it is only driven when a 64-bit master and target are both negotiating 64-bit transfers.

Signals

• AD[31:0] — Multiplexed address/data bus; during the address phase carries the target address; during data phase carries read or write data (per PCI Local Bus Specification).
• AD[63:32] — Upper 32 bits of the optional 64-bit extension; carried on the top-section connector.
• C/BE[3:0]# — Command/byte-enable lines; during the address phase encode the bus command; during the data phase indicate which byte lanes are active.
• C/BE[7:4]# — Upper byte-enables for 64-bit transfers; carried on the top-section connector.
• PAR — Even parity over AD[31:0] and C/BE[3:0]#; generated by the current bus master or target one cycle after the AD/C/BE signals.
• PAR64 — Even parity over AD[63:32] and C/BE[7:4]# during 64-bit transfers; only valid when REQ64# and ACK64# have been asserted.
• FRAME# — Driven by the current initiator to indicate that a bus transaction is in progress; deasserted during the final data phase.
• IRDY# — Initiator Ready; asserted by the master to indicate it is ready to complete the current data phase.
• TRDY# — Target Ready; asserted by the target to indicate it is ready to complete the current data phase.
• STOP# — Asserted by the target to request the initiator end the current transaction.
• DEVSEL# — Device Select; asserted by the target that has decoded its address.
• LOCK# — Resource Lock; used by a master to perform an indivisible read-modify-write sequence across multiple transactions.
• FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK# — All open-drain with pull-up resistors on the System Slot.
• PERR# — Parity Error; asserted two cycles after a data phase in which a parity error was detected.
• SERR# — System Error; used to report address parity errors or other critical errors; open-drain.
• REQ64# — Request 64-bit transfer; asserted by a 64-bit master simultaneously with FRAME# to request 64-bit operation; sustained tri-state.
• ACK64# — Acknowledge 64-bit transfer; asserted by a 64-bit target simultaneously with DEVSEL# to accept 64-bit operation; sustained tri-state.
• REQn# / GNTn# — Bus request and grant pairs for each PCI agent on the backplane (REQ1–REQ4, GNT1–GNT4); arbitrated by the System Slot.
• CLKn — PCI bus clock outputs distributed from the System Slot to each peripheral slot (CLK1–CLK4); 33 MHz or 66 MHz.
• CLKM — Module bus clock (Module Bus Slot only); provides a dedicated clock to the module bus agent.
• M66EN — 66 MHz enable; when pulled high by the backplane indicates all agents support 66 MHz operation; enables the optional 66 MHz bus speed.
• RST# — PCI bus reset; deasserted by the System Slot to initialise all agents after power-on or system reset.
• RSTIN# — Reset input to the System Slot; driven by an external reset source; 330 Ω pull-up on the System Slot.
• INTA#, INTB#, INTC#, INTD# — PCI interrupt request lines; open-drain, active low; routed to the System Slot interrupt controller.
• NMI# — Non-Maskable Interrupt; asserted to signal a non-recoverable hardware error to the CPU.
• SDONE — Snoop Done; asserted by the cache controller on the System Slot to indicate a cache snoop has completed.
• SBO# — Snoop Backoff; asserted together with SDONE to indicate the snooped cache line is dirty and must be written back.
• IDSEL0 / IDSEL1 / IDSEL2 — Initialisation Device Select; used during configuration read/write cycles to select individual PCI agents on the backplane.
• SLEEP#/SDAT — Dual-function pin: sleep control signal or I²C serial data (SDA) line for system management.
• ICPEN#/SCLK — Dual-function pin: ICP enable or I²C serial clock (SCL) line for system management.
• USB+ / USB- — USB differential data lines (+D and −D) routed through the backplane to USB devices.
• VBATT — Battery-backed power rail for real-time clock or non-volatile memory retention.
• V(I/O) — Signalling supply; +3.3 V on 3.3 V boards or +5 V on 5 V boards; determines the I/O logic levels.
• OSC (PWDN) — Oscillator or power-down control signal; function is board-specific.
• Xn — Reserved pins (X1–X12); must not be connected by add-in cards; available for future PICMG 1.0 revisions.

References

• PCI Local Bus Specification, Revision 2.2 (December 1998) — PCI-SIG, archived by Bitsavers / Internet Archive
• PCI Local Bus Specification, Revision 2.1 (June 1995) — PCI-SIG, archived by Bitsavers / Internet Archive
• MARK SOKOS (sokos@desupernet.net)

Category:Buses Connectors