PCI Express 1x - 64 pin Female Connector
PCI Express (PCIe) is a serial point-to-point expansion bus standard governed by the PCI Special Interest Group (PCI-SIG), introduced in 2003 as the successor to the parallel PCI bus. The x4 variant uses a 64-pin card-edge connector (32 contacts on each of Side A and Side B) at 1.0 mm contact pitch, carrying four differential transmit/receive lane pairs. Power is supplied on +12 V and +3.3 V rails, and the interface supports speeds of 2.5 GT/s (Gen 1), 5.0 GT/s (Gen 2), and 8.0 GT/s (Gen 3) on the same connector, as defined in the PCI Express Card Electromechanical Specification, Revision 3.0 (July 2013). An x4 card may be inserted into an x8 or x16 slot and will operate at x4 link width.
| Pin | Side B Connector | Side A Connector |
|---|---|---|
| # | Name | Description |
| 1 | +12v | +12 volt power |
| 2 | +12v | +12 volt power |
| 3 | RSVD | Reserved |
| 4 | GND | Ground |
| 5 | SMCLK | SMBus clock |
| 6 | SMDAT | SMBus data |
| 7 | GND | Ground |
| 8 | +3.3v | +3.3 volt power |
| 9 | JTAG1 | +TRST# |
| 10 | 3.3Vaux | 3.3v volt power |
| 11 | WAKE# | Link Reactivation |
| 12 | RSVD | Reserved |
| 13 | GND | Ground |
| 14 | HSOp(0) | Transmitter Lane 0, Differential pair |
| 15 | HSOn(0) | GND |
| 16 | GND | Ground |
| 17 | PRSNT#2 | Hotplug detect |
| 18 | GND | Ground |
| 19 | HSOp(1) | Transmitter Lane 1, Differential pair |
| 20 | HSOn(1) | GND |
| 21 | GND | Ground |
| 22 | GND | Ground |
| 23 | HSOp(2) | Transmitter Lane 2, Differential pair |
| 24 | HSOn(2) | GND |
| 25 | GND | Ground |
| 26 | GND | Ground |
| 27 | HSOp(3) | Transmitter Lane 3, Differential pair |
| 28 | HSOn(0) | GND |
| 29 | GND | Ground |
| 30 | RSVD | Reserved |
| 31 | PRSNT#2 | Hot plug detect |
| 32 | GND | Ground |
Notes
- The x4 connector has 64 pins total (32 per side), physically shorter than x8 (98 pins) and x16 (164 pins) but longer than x1 (36 pins). All PCIe slots share the same 1.0 mm contact pitch.
- An x4 add-in card inserted into a larger slot (x8 or x16) will negotiate to x4 link width and operate correctly; likewise, an x1 card will work at x1 speed in an x4 slot.
- Power rails: +12 V (pins 1–2, Side B) and +3.3 V (pin 8, Side B) with 3.3 Vaux (pin 10, Side B) for auxiliary standby power.
- PRSNT1# and PRSNT2# are presence-detect pins used by the system to confirm a card is seated; WAKE# enables the card to reactivate a link from a low-power state.
- PERST# (system reset to card) and REFCLK+/- (100 MHz differential reference clock) are carried on Side A of the connector; SMCLK/SMDAT provide an SMBus management interface.
- The connector is mechanically and electrically defined by the PCI Express Card Electromechanical Specification, Revision 3.0 (PCI-SIG, July 2013).
Signals
- +12V — main 12 V power supply to the add-in card
- 3.3Vaux — 3.3 V auxiliary power, remains live when the main supply is off (supports WAKE#)
- +3.3V — 3.3 V main power rail
- GND — signal and power ground
- RSVD — reserved; must not be connected by add-in cards
- SMCLK — SMBus clock; used for out-of-band management and power management communication
- SMDAT — SMBus data
- JTAG1 (+TRST#) — JTAG test reset signal (part of the JTAG boundary-scan chain)
- WAKE# — open-drain signal from card to system requesting link reactivation from a low-power state
- PRSNT#2 — presence-detect signal; pulled low by the card to indicate it is inserted; also used for hot-plug detection
- HSOp(n) / HSOn(n) — high-speed transmitter differential pair, positive and negative, for lane n (n = 0–3); these are the PCIe TX lanes from the card’s perspective