Zorro II/III

The Zorro II and Zorro III expansion buses share a single 100-pin edge connector introduced with the Commodore Amiga 2000 in 1987. Zorro II presents a buffered version of the Motorola 68000 bus: 16-bit data (D15–D0), 24-bit address (A23–A1), clocked at 7.16 MHz with a four-clock basic bus cycle. Zorro III, first shipped in the Amiga 3000 (1990) and designed by Dave Haynie at Commodore Systems Engineering, extends this to a 32-bit data bus, 32-bit address bus, and a peak burst transfer rate of approximately 37.5 MB/s, while remaining physically and electrically backward-compatible with Zorro II cards. Each physical pin carries up to three distinct logical signal names — one for Zorro II mode, one for the Zorro III address phase, and one for the Zorro III data phase — and an expansion card asserts ZORRO3* (SenseZ3, pin 91) to claim Zorro III operation; without that assertion the slot defaults to Zorro II compatibility mode. AutoConfig, implemented via the CONFIGIN*/CONFIGOUT* daisy-chain (pins 12/11), allows each card to identify itself and be automatically mapped into the Amiga address space at boot.

Notes

• The connector is a 100-pin single-piece (non-edge-card-split) bus connector; the Amiga 2000 contains seven Zorro II slots, the Amiga 3000 contains four Zorro III-capable slots that accept Zorro II cards without modification, and the Amiga 4000 also uses Zorro III slots.
• Pin 91 (SenseZ3) is grounded on the backplane for Zorro III-capable slots; a card reads this pin to determine whether it may assert Zorro III mode. On Zorro II-only backplanes the pin is not grounded and the card operates in Zorro II compatibility mode.
• All signal lines are 5 V TTL-compatible logic levels. Active-low signals are indicated by a leading slash (/) in the physical and logical names.
• Power available per slot: +5 V, +12 V, and −12 V rails. The −5 V rail (pin 8) is present for legacy compatibility.
• Pins 40, 42, 44, and 96 are labelled Reserved in Zorro III mode; their Zorro II parenthetical names (/EINT7, /EINT5, /EINT4, /EINT1) were optional external interrupt lines never widely used.
• Bus arbitration and DMA mastering are fully supported in Zorro III via the /BRn, /BGn, /BGACK signal group and the /MTCR//MTACK handshake for memory transfer cycles.

Signals

• Ground (pins 1–4, 13, 25, 37, 49, 61, 73, 85, 87–90, 99–100) — common ground reference
• +5VDC (pins 5–6) — +5 V supply to expansion card
• /OWN (pin 7) — slot ownership: asserted by the card currently driving the bus
• -5VDC (pin 8) — −5 V supply (legacy; limited current)
• /SLAVEn (pin 9) — slave select: card asserts this to claim a bus cycle addressed to it
• +12VDC (pin 10) — +12 V supply to expansion card
• /CFGOUTn (pin 11) — AutoConfig output: passed to the next card in the CONFIGOUT/CONFIGIN daisy-chain once this card has been configured
• /CFGINn (pin 12) — AutoConfig input: received from the previous card (or from the host if this is the first slot); card responds to AutoConfig cycles only when asserted
• /C3 Clock (pin 14) — 3.58 MHz colour clock, inverted phase
• CDAC Clock (pin 15) — colour DAC clock (3.58 MHz, used for chip-set timing)
• /C1 Clock (pin 16) — 3.58 MHz colour clock, primary phase
• /CINH / /OVR (pin 17) — Zorro III: /CINH (cache inhibit, prevents CPU caching of this address range); Zorro II: /OVR (override, allows card to override chip RAM)
• /MTCR / XRDY (pin 18) — Zorro III: /MTCR (memory transfer cycle request, DMA handshake); Zorro II: XRDY (external ready, extends bus cycle)
• /INT2 (pin 19) — interrupt level 2 request (open-drain, shared across all slots)
• -12VDC (pin 20) — −12 V supply to expansion card
• A5–A23 / A24–A31 (address lines) — Zorro II: A1–A23 (24-bit); Zorro III address phase: A1–A31 (32-bit); shared with AD-prefixed pins in Zorro III data phase
• /INT6 (pin 22) — interrupt level 6 request (open-drain, shared across all slots)
• /LOCK (pin 29) — Zorro III: bus lock (prevents another master from stealing the bus mid-cycle); Zorro II: carries A1
• AD8–AD31 (pins 30–84, selected) — multiplexed address/data lines; in Zorro II these carry address bits A8–A23 and data bits D8–D15; in Zorro III address phase they carry A8–A31; in Zorro III data phase they carry D0–D31
• FC0–FC2 (pins 31, 33, 35) — 68000/68030 function codes indicating the processor state (user/supervisor, data/program)
• E Clock (pin 50) — 6800-family enable clock (~0.894 MHz), derived from the 7 MHz system clock; used by legacy 6800-bus peripherals
• /DS0, /DS1, /DS2, /DS3 (pins 51, 98, 70, 72) — data strobes for each byte lane of the 32-bit data bus; Zorro II uses /LDS and /UDS (lower/upper data strobe) mapped to /DS2 and /DS3
• /RESET (pin 53) — system reset (open-drain); driving this line low resets the entire system
• /HLT (pin 55) — system halt; asserted by the CPU on a double-bus fault
• /BRn (pin 60) — bus request: asserted by a card wishing to become bus master (DMA)
• /BGACK (pin 62) — bus grant acknowledge: asserted by the card that has taken control of the bus
• /BGn (pin 64) — bus grant: asserted by the current bus master to pass mastership to the requesting card
• /DTACK (pin 66) — data transfer acknowledge: asserted by the addressed slave to terminate a bus cycle
• READ (pin 68) — cycle direction indicator: high = read cycle, low = write cycle
• /CCS (pin 74) — cycle start strobe (Zorro III address strobe, equivalent to 68000 /AS in Zorro II)
• SD0–SD7 (pins 75–86, selected) — supplemental data lines D0–D7 in Zorro II; reserved in Zorro III address phase; carry D16–D23 in Zorro III data phase
• SenseZ3 (pin 91) — tied to ground by the backplane on Zorro III-capable slots; read by the card to determine whether Zorro III operation is permitted
• 7M (pin 92) — 7.16 MHz system clock (also called E7M in Zorro II context)
• DOE (pin 93) — data output enable: indicates the bus driver direction for data lines
• /IORST (pin 94) — I/O reset (Zorro III); equivalent to /BUSRST in Zorro II; resets expansion card logic without resetting the CPU
• /BCLR (pin 95) — bus clear (Zorro III); equivalent to /GBG (grant bus grant) in Zorro II; forces the current DMA master to release the bus
• /FCS (pin 97) — full cycle strobe (Zorro III); not connected in Zorro II; used to indicate a complete address+data bus cycle in Zorro III burst transfers
• /MTACK (pin 48) — Zorro III: memory transfer acknowledge (DMA handshake response to /MTCR); Zorro II: /VPA (valid peripheral address, for 6800-bus cycles)
• /BERR (pin 46) — bus error: asserted when a bus cycle cannot be completed (no slave response, timeout, or parity error)

References

• Amiga Hardware Reference Manual, 3rd Edition — Commodore-Amiga Inc., 1991; Appendix K documents the complete Zorro II and Zorro III bus architecture
• The Zorro III Bus Specification — Dave Haynie, Commodore A3000 Systems Engineering; canonical engineering specification for the Zorro III bus
• Commodore Amiga A500–A2000 Technical Reference Manual — Commodore, 1987; Section 3.4 covers the 100-pin expansion connector in the A2000

Category:Buses Connectors