VESA Local Bus

The VESA Local Bus (VL-Bus) is a 32-bit local bus standard developed by the Video Electronics Standards Association; version 1.0 was ratified in August 1992 and version 2.0 published in November 1993. It was designed to give expansion cards — primarily graphics adaptors and IDE/SCSI controllers — direct access to the Intel 486 CPU bus at the processor’s own clock speed, reaching up to 50 MHz in slot implementations and 66 MHz for on-board devices. The bus uses a 58-pin edge connector appended inline after an ISA slot, so a card may span both connectors whilst the VL-Bus section operates independently of the ISA portion. An optional 64-bit extension multiplexes the upper data lines (D32–D63) across existing pins rather than adding a separate connector, and burst transfers using *BLAST/*BRDY signals could sustain very high throughput; the standard was superseded by PCI before it could adapt to the Pentium’s split-bus architecture.

58 PIN EDGE CONNECTOR MALE at the card.

58 PIN EDGE CONNECTOR FEMALE at the computer.

Signal Descriptions

• A2-A31: Address Bus
• ADS: Address Strobe
• BE0-BE3: Byte Enable. Indicates that the 8 data lines corresponding to each signal will deliver valid data.
• BLAST: Burst Last. Indicates a VLB Burst Cycle, which will complete with *BRDY. The VLB Burst cycle consists of an address phase followed by four data phases.
• BRDY: Burst Ready. Indicates the end of the current burst transfer.
• D0-D31: Data Bus. Valid bytes are indicated by *BE(x) signals.
• D/C: Data/Command. Used with M/IO and W/R to indicate the type of cycle.

• ID0-ID4: Identification Signals.

• IRQ9: Interrupt Request. Connected to IRQ9 on ISA bus. This allows standalone VLB adapters (not connected to ISA portion of the bus) to have one IRQ.
• LEADS: Local Enable Address Strobe. Set low by VLB master (not CPU). Also used for cache invalidation signal.
• LBS16: Local Bus Size 16. Used by slave device to indicate that it has a transfer width of only 16 bits.
• LCLK: Local Clock. Runs at the same frequency as the cpu, up to 50 MHz. 66 MHz is allowed for on-board devices.
• LDEV: Local Device: When appropriate address and M/IO signals are present on the bus, the VLB device must pull this line low to indicate that it is a VLB device. The VLB controller will then use the VLB bus for the transfer.
• LRDY: Local Ready. Indicates that the VLB device has completed the cycle. This signal is only used for single cycle transfers. *BRDY is used for burst transfers.
• LGNT: Local Grant. Indicates that an *LREQ signal has been granted, and control is being transferred to the new VLB master.
• LREQ: Local Request. Used by VLB Master to gain control of the bus.
• M/IO: Memory/IO. See D/C for signal description.
• RDYRTN: Ready Return. Indicates VLB cycle has been completed. May precede LRDY by one cycle.
• RESET: Reset. Resets all VLB devices.
• WBACK: Write Back.

64-bit Expansion Signals

• ACK64: Acknowledge 64 bit transfer. Indicates that the device can perform the requested 64 bit transfer cycle.
• BE4-BE7: Byte Enable. Indicates which bytes are valid (similar to BE0-BE3).
• D32-D63: Upper 32 bits of data bus. Multiplexed with address bus.
• LBS64: Local Bus Size 64 bits. Used by VLB Master to indicate that it desires a 64 bit transfer.
• W/R: Write/Read. See D/C for signal description.

References

• VESA VL-Bus Local Bus Standard Version 2.0 (November 1993)
• VESA VL-Bus Signal Reference

Category:Buses Connectors