NuBus 90

NuBus-90 (proposed IEEE P1196-R1990) is an upward-compatible extension of the original NuBus standard (IEEE 1196-1987), itself a 32-bit synchronous multimaster backplane bus developed at MIT in 1978–1979 and commercialised by Texas Instruments. Whilst the standard NuBus operates at 10 MHz with burst throughputs of up to 40 MB/s, NuBus-90 introduces a second clock line (/CLK2X) running at 20 MHz for card-to-card block transfers, raising peak throughput to approximately 70 MB/s. The physical connector is unchanged: a 96-pin DIN 41612 (Euro-DIN) three-row connector (rows A, B, C; 32 pins per row; 2.54 mm pitch), with the male plug on the card edge and the female receptacle on the backplane. Apple adopted NuBus-90 in the Macintosh Quadra series (900 and 950), implementing the double-speed transfer signals whilst leaving the cache-coherency (/CM0–/CM2, /CBUSY) and serial-bus (SB0, SB1) signals bused and terminated on the backplane but not driven by Quadra host logic; the proposal was never formally ratified as a completed IEEE standard.

96-pin DIN 41612 three-row (Euro-DIN) connector — male plug at card edge; female receptacle on backplane

Row A

Row B

Row C

Notes

• The physical connector is identical to standard NuBus: a 96-pin DIN 41612 (Euro-DIN / IEC 60603-2) three-row connector, 2.54 mm (0.1 inch) pitch. NuBus-90 expansion slots are backward-compatible; standard 10 MHz NuBus cards operate normally in NuBus-90 slots.
• NuBus-90 was a proposal (IEEE P1196-R1990) and was never formally ratified as a completed IEEE standard. The parent IEEE 1196-1987 standard was itself withdrawn on 6 March 2000.
• The Macintosh Quadra 900 and 950 implement NuBus-90 only partially: card-to-card double-speed transfers at 20 MHz are supported via /CLK2X and /CLK2XEN, but the Quadra’s NuBus host controller communicates with main memory at 10 MHz — double-speed transfers to or from main memory are not available.
• Cache-coherency signals /CM0, /CM1, /CM2, and /CBUSY are physically present on the connector and are bused and terminated on the Quadra backplane, but are not driven or monitored by Quadra host logic.
• SB0 (Row A, pin 2) and SB1 (Row C, pin 2) occupy formerly reserved pins and define a high-speed serial bus in the NuBus-90 proposal. On the Quadra 900 these signals are bused and terminated but not driven by the main board.
• STDBYPWR (Row B, pin 25) supplies a small +5 V trickle current to modem expansion cards to enable standby detection whilst the system is powered down.
• Row B in standard NuBus carried only power and ground on pins 1–7 and 28–32; NuBus-90 repurposes Row B pins 8–11 (/TM2, /CM0, /CM1, /CM2) and pins 24–27 (/CLK2X, STDBYPWR, /CLK2XEN, /CBUSY) for its new control signals.

Signals

• /AD0–/AD31 — 32 multiplexed address/data lines; active-low; carry the bus address on the first cycle and data on subsequent cycles of a transaction
• /ACK — Acknowledge; asserted by the responding agent to indicate a successful transfer or to signal an error condition
• /ARB0–/ARB3 — Four-wire arbitration bus; used for fair, distributed arbitration between bus masters
• /CBUSY — Cache Busy (NuBus-90); asserted by a card to indicate that its cache is in the process of a coherency operation; not driven by Quadra host logic
• /CLK — Bus clock; 10 MHz synchronous clock distributed to all slots
• /CLK2X — Double-speed clock (NuBus-90); 20 MHz clock enabling card-to-card block transfers at double the standard rate; not used for transfers to main memory on Quadra hardware
• /CLK2XEN — CLK2X driver enable (NuBus-90); asserted by the bus master to enable the /CLK2X driver for a double-speed block transfer
• /CM0, /CM1, /CM2 — Cache coherency mode bits 0–2 (NuBus-90); define the cache coherency protocol for a transaction; not driven or monitored by Quadra host logic
• /ID0–/ID3 — Slot identification lines; each slot ties its ID lines to a unique four-bit value, allowing cards to self-identify their slot address at startup
• /NMRQ — Non-Master Request; allows non-bus-master cards (e.g. interrupt controllers) to request attention from the bus master
• /PFW — Power Fail Warning; asserted by the system when mains power is failing, giving cards time to save state
• /RESET — Bus reset; asserted by the system to initialise all bus agents
• /RQST — Bus Request; asserted by a card to request ownership of the bus
• SB0 — Serial Bus line 0 (NuBus-90, Row A pin 2); one conductor of the proposed high-speed serial bus; formerly a reserved (no-connect) pin in standard NuBus
• SB1 — Serial Bus line 1 (NuBus-90, Row C pin 2); the complementary conductor of the serial bus; formerly reserved in standard NuBus
• /SP — Slot Parity; provides parity checking over the AD bus
• /SPV — Slot Parity Valid; indicates that the parity information on /SP is valid for the current cycle
• /START — Transfer Start; asserted by the bus master at the beginning of a bus cycle to indicate that a valid address is on the AD lines
• STDBYPWR — Standby Power (NuBus-90, Row B pin 25); supplies a small +5 V trickle current to modem cards for standby detection whilst the main system is powered off
• /TM0, /TM1 — Transaction Mode bits 0 and 1; encode the type of bus transaction (read, write, block read, block write, etc.)
• /TM2 — Transaction Mode bit 2 (NuBus-90, Row B pin 8); when asserted in conjunction with /TM0 and /TM1, requests a double-speed block transfer at 20 MHz

References

• IEEE 1196-1987 — IEEE Standard for a Simple 32-Bit Backplane Bus: NuBus
• NuBus Specification (Document 2242825-0001, 1983) — Texas Instruments via Bitsavers
• Designing Cards and Drivers for the Macintosh Family, Third Edition — Apple Computer / Addison-Wesley, 1992.
• Macintosh Quadra 900 Developer Note — Apple Computer, Developer Technical Publications.

Category:Buses Connectors