PCI Express x16 — 164-contact (82 per side) edge connector
PCI Express (PCIe) is a high-speed serial expansion interface maintained by the PCI Special Interest Group (PCI-SIG); the base specification was published in 2002 and the bus reached mainstream PCs in 2003–2004. It replaces the shared parallel bus of conventional PCI with point-to-point serial links. A link is built from lanes, each lane being one differential pair per direction (dual-simplex); a x16 slot provides 16 lanes and is the format used by graphics cards. First-generation PCIe runs at 2.5 GT/s per lane per direction and the second generation at 5.0 GT/s, using 8b/10b encoding with an embedded clock. The x16 add-in card edge connector has 164 contacts, 82 on each side. The table below lists the Side B contacts.
| Pin | Name | Description |
|---|---|---|
| 1 | +12v | +12 volt power |
| 2 | +12v | +12 volt power |
| 3 | RSVD | Reserved |
| 4 | GND | Ground |
| 5 | SMCLK | SMBus clock |
| 6 | SMDAT | SMBus data |
| 7 | GND | Ground |
| 8 | +3.3v | +3.3 volt power |
| 9 | JTAG1 | +TRST# |
| 10 | 3.3Vaux | 3.3v volt power |
| 11 | WAKE# | Link Reactivation |
| 12 | RSVD | Reserved |
| 13 | GND | Ground |
| 14 | HSOp(0) | Transmitter Lane 0, Differential pair |
| 15 | HSOn(0) | GND |
| 16 | GND | Ground |
| 17 | PRSNT#2 | Hotplug detect |
| 18 | GND | Ground |
| 19 | HSOp(1) | Transmitter Lane 1, Differential pair |
| 20 | HSOn(1) | GND |
| 21 | GND | Ground |
| 22 | GND | Ground |
| 23 | HSOp(2) | Transmitter Lane 2, Differential pair |
| 24 | HSOn(2) | GND |
| 25 | GND | Ground |
| 26 | GND | Ground |
| 27 | HSOp(3) | Transmitter Lane 3, Differential pair |
| 28 | HSOn(3) | Transmitter Lane 3, differential pair (−) |
| 29 | GND | Ground |
| 30 | RSVD | Reserved |
| 31 | PRSNT#2 | Hot plug detect |
| 32 | GND | Ground |
| 33 | HSOp(4) | Transmitter Lane 4, Differential pair |
| 34 | HSOn(4) | GND |
| 35 | GND | Ground |
| 36 | GND | Ground |
| 37 | HSOp(5) | Transmitter Lane 5, Differential pair |
| 38 | HSOn(5) | GND |
| 39 | GND | Ground |
| 40 | GND | Ground |
| 41 | HSOp(6) | Transmitter Lane 6, Differential pair |
| 42 | HSOn(6) | GND |
| 43 | GND | Ground |
| 44 | GND | Ground |
| 45 | HSOp(7) | Transmitter Lane 7, Differential pair |
| 46 | HSOn(7) | GND |
| 47 | GND | Ground |
| 48 | PRSNT#2 | Hot plug detect |
| 49 | GND | Ground |
| 50 | HSOp(8) | Transmitter Lane 8, Differential pair |
| 51 | HSOn(8) | GND |
| 52 | GND | Ground |
| 53 | GND | Ground |
| 54 | HSOp(9) | Transmitter Lane 9, Differential pair |
| 55 | HSOn(9) | GND |
| 56 | GND | Ground |
| 57 | GND | Ground |
| 58 | HSOp(10) | Transmitter Lane 10, Differential pair |
| 59 | HSOn(10) | GND |
| 60 | GND | Ground |
| 61 | GND | Ground |
| 62 | HSOp(11) | Transmitter Lane 11, Differential pair |
| 63 | HSOn(11) | GND |
| 64 | GND | Ground |
| 65 | GND | Ground |
| 66 | HSOp(12) | Transmitter Lane 12, Differential pair |
| 67 | HSOn(12) | GND |
| 68 | GND | Ground |
| 69 | GND | Ground |
| 70 | HSOp(13) | Transmitter Lane 13, Differential pair |
| 71 | HSOn(13) | GND |
| 72 | GND | Ground |
| 73 | GND | Ground |
| 74 | HSOp(14) | Transmitter Lane 14, Differential pair |
| 75 | HSOn(14) | GND |
| 76 | GND | Ground |
| 77 | GND | Ground |
| 78 | HSOp(15) | Transmitter Lane 15, Differential pair |
| 79 | HSOn(15) | GND |
| 80 | GND | Ground |
| 81 | PRSNT#2 | Hot plug present detect |
| 82 | RSVD | Reserved |
Notes
- A mechanical key between pins 11 and 12 sets the card’s orientation and prevents incorrect insertion.
- The table lists the Side B contacts — the side carrying the transmitter pairs, SMBus, WAKE# and present-detect pins. Side A carries the receiver pairs (PERp/PERn), the +12 V and +3.3 V rails, the 100 MHz reference clock (REFCLK+/REFCLK−), the PERST# reset and the JTAG TCK/TDI/TDO/TMS pins.
- Each HSOp(n)/HSOn(n) pair is the positive and negative half of one transmit lane’s differential pair (named PETp/PETn in the specification); two ground pins separate adjacent pairs to limit crosstalk.
- Up-plugging: the slot lengths nest (x1 ends at pin 18, x4 at 32, x8 at 49, x16 at 82), so a shorter card seats in the front of a longer slot. A longer card cannot be forced into a shorter slot.
- The multiple PRSNT#2 pins (17, 31, 48, 81) together with PRSNT1# let the system detect card length and support hot-plug power sequencing.
- A x16 card draws up to 75 W through the slot (combined +12 V and +3.3 V); higher-power graphics cards take additional power from separate 6-pin or 8-pin PCIe power connectors.
Signals
- HSOp(n) / HSOn(n) (PETp/PETn) — positive and negative halves of transmit Lane n’s differential pair.
- PRSNT#2 — hot-plug present-detect; multiple instances allow card-length and up-plug detection.
- WAKE# — sideband signal that requests link reactivation from a low-power state.
- SMCLK / SMDAT — System Management Bus (SMBus) clock and data for out-of-band management.
- 3.3Vaux — auxiliary 3.3 V supply, available for wake/management when the main rails are off.
- JTAG1 (TRST#) — JTAG Test Access Port reset; the remaining JTAG pins (TCK/TDI/TDO/TMS) are on Side A.
- +12v / +3.3v — main power rails.
References
- PCI Express Base Specification, Revision 2.0 (PCI-SIG) — serial-link architecture and per-lane data rates (Internet Archive scan).
- PCI Express Card Electromechanical (CEM) Specification, Revision 2.0 (PCI-SIG) — x16 connector pinout, present-detect and up-plugging rules.