Sun
SBus - 96 pin female connector (Fujitsu FCN 234P096-G/Y)
| Pin | Name | Description |
|---|---|---|
| 1 | GND | Ground |
| 2 | sb_br* | sb_br |
| 3 | sb_sel* | sb_sel |
| 4 | sb_irql* | ? |
| 5 | sb_d(0) | Data bit 0 |
| 6 | sb_d(2) | Data bit 2 |
| 7 | sb_d(4) | Data bit 4 |
| 8 | sb_irq2* | Interrupt Request 2 |
| 9 | sb_d(6) | Data bit 6 |
| 10 | sb_d(8) | Data bit 8 |
| 11 | sb_d(10) | Data bit 10 |
| 12 | sb_irq3* | Interrupt Request 3 |
| 13 | sb_d(12) | Data bit 12 |
| 14 | sb_d(14) | Data bit 14 |
| 15 | sb_d(16) | Data bit 16 |
| 16 | sb_irq4* | Interrupt Request 4 |
| 17 | sb_d(19) | Data bit 19 |
| 18 | sb_d(21) | Data bit 21 |
| 19 | sb_d(23) | Data bit 23 |
| 20 | sb_irq5* | Interrupt Request 5 |
| 21 | sb_d(25) | Data bit 25 |
| 22 | sb_d(27) | Data bit 27 |
| 23 | sb_d(29) | Data bit 29 |
| 24 | sb_irq6* | Interrupt Request 6 |
| 25 | sb_d(31) | Data bit 31 |
| 26 | sb_siz(0) | sb_siz(0 |
| 27 | sb_siz(2) | sb_siz(2 |
| 28 | sb_irq7* | Interrupt Request 7 |
| 29 | sb_a(0) | Address bit 0 |
| 30 | sb_a(2) | Address bit 2 |
| 31 | sb_a(4) | Address bit 4 |
| 32 | sb_merr* | sb_merr |
| 33 | sb_a(6) | Address bit 6 |
| 34 | sb_a(8) | Address bit 8 |
| 35 | sb_a(10) | Address bit 10 |
| 36 | sb_err* | sb_err |
| 37 | sb_pa(12) | Address bit 12 |
| 38 | sb_pa(14) | Address bit 14 |
| 39 | sb_pa(16) | Address bit 16 |
| 40 | sb_ack8* | sb_ack8 |
| 41 | sb_pa(18) | Address bit 18 |
| 42 | sb_pa(20) | Address bit 20 |
| 43 | sb_pa(22) | Address bit 22 |
| 44 | sb_ack32* | sb_ack32 |
| 45 | sb_pa(24) | Address bit 24 |
| 46 | sb_pa(26) | Address bit 26 |
| 47 | N/C | Not connected |
| 48 | -12V | -12 VDC |
| 49 | sb_clk | Clock |
| 50 | sb_bg* | sb_bg |
| 51 | sb_as* | sb_as |
| 52 | GND | Ground |
| 53 | sb_d(1) | Data bit 1 |
| 54 | sb_d(3) | Data bit 3 |
| 55 | sb_d(5) | Data bit 5 |
| 56 | +5V | +5 VDC |
| 57 | sb_d(7) | Data bit 7 |
| 58 | sb_d(9) | Data bit 9 |
| 59 | sb_d(11) | Data bit 11 |
| 60 | GND | Ground |
| 61 | sb_d(13) | Data bit 13 |
| 62 | sb_d(15) | Data bit 15 |
| 63 | sb_d(17) | Data bit 17 |
| 64 | +5V | +5 VDC |
| 65 | sb_d(18) | Data bit 18 |
| 66 | sb_d(20) | Data bit 20 |
| 67 | sb_d(22) | Data bit 22 |
| 68 | GND | Ground |
| 69 | sb_d(24) | Data bit 24 |
| 70 | sb_d(26) | Data bit 26 |
| 71 | sb_d(28) | Data bit 28 |
| 72 | +5V | +5 VDC |
| 73 | sb_d(30) | Data bit 30 |
| 74 | sb_siz(1) | sb_siz(1 |
| 75 | sb_rd | sb_rd |
| 76 | GND | Ground |
| 77 | sb_a(1) | Address bit 1 |
| 78 | sb_a(3) | Address bit 3 |
| 79 | sb_a(5) | Address bit 5 |
| 80 | +5V | +5 VDC |
| 81 | sb_a(7) | Address bit 7 |
| 82 | sb_a(9) | Address bit 9 |
| 83 | sb_a(11) | Address bit 11 |
| 84 | GND | Ground |
| 85 | sb_pa(13) | Address bit 13 |
| 86 | sb_pa(15) | Address bit 15 |
| 87 | sb_pa(17) | Address bit 17 |
| 88 | +5V | +5 VDC |
| 89 | sb_pa(19) | Address bit 19 |
| 90 | sb_pa(21) | Address bit 21 |
| 91 | sb_pa(23) | Address bit 23 |
| 92 | GND | Ground |
| 93 | sb_pa(25) | Address bit 25 |
| 94 | sb_pa(27) | Address bit 27 |
| 95 | sb_reset* | Reset |
| 96 | +12V | +12 VDC |
[The following article is licensed under the GNU Free Documentation License. It reproduces the Wikipedia article “MSBus”] SBus is a computer bus system that was used in most SPARC-based computers from Sun Microsystems during the 1990s. It was introduced in 1989 to be a high-speed bus counterpart to their high-speed SPARC processors, replacing the earlier (and by this time, outdated) VMEbus that had been used in their earlier Motorola 68030-based systems and early SPARC boxes. When Sun was attempting to “open” the SPARC in the early 1990s, SBus was likewise standardized and became IEEE-1496. In 1997 Sun started to migrate away from SBus onto PCI, and today SBus is no longer used. SBus is in many ways a “clean” design. It was targeted only to the SPARC so many cross-platform issues were simply not a consideration. SBus was based on a big-endian 32-bit address and data bus, can run at speeds ranging from 16.6MHz to 25MHz, and is capable of transferring up to 100Mbyte/second. Devices are each mapped onto a 28-bit address space (16 megabytes). Only eight masters are supported, although there are an unlimited number of slaves. When the 64-bit UltraSPARC was introduced SBus was modified to use clock-doubling and transfer two 32-bit data words per cycle to produce a 200MByte/s 64-bit bus. For contrast, modern 66MHz/64-bit PCI is 528MByte/s. This variant of the SBus architecture used the same connector as the older one, unlike the various versions of PCI. SBus was a peripheral interconnect only (like PCI). Sun systems used another standardized system as a CPU-memory bus, MBus.