NuBus is a 32-bit synchronous multimaster backplane bus standardised as IEEE 1196-1987, using a 96-pin DIN 41612 connector, operating at 10 MHz.
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NuBus is a 32-bit synchronous multimaster backplane bus originally developed at MIT (1978–1979) by Professor Steve Ward and colleagues as part of the NuMachine workstation project, then commercialised by Texas Instruments for its Explorer Lisp workstation in 1983. The bus was standardised as IEEE 1196-1987 (ANSI approved February 1988, withdrawn March 2000) and operates at 10 MHz, yielding a maximum burst throughput of 40 MB/s. Apple adopted NuBus as the expansion interface for the Macintosh II family (1987–1993), fitting six slots in the Mac II, IIx, and IIfx, and three slots in the IIcx and IIci. The physical connector is a 96-pin DIN 41612 (Euro-DIN / IEC 60603-2) three-row connector with 32 pins per row (rows A, B, C) on a 2.54 mm pitch; the card edge carries a male plug and the backplane carries the female receptacle.
Row A
Pin
Name
Description
1
-12 V
-12 VDC
2
-
3
/SPV
4
/SP
5
/TM1
6
/AD1
Address/Data 1
7
/AD3
Address/Data 3
8
/AD5
Address/Data 5
9
/AD7
Address/Data 7
10
/AD9
Address/Data 9
11
/AD11
Address/Data 11
12
/AD13
Address/Data 13
13
/AD15
Address/Data 15
14
/AD17
Address/Data 17
15
/AD19
Address/Data 19
16
/AD21
Address/Data 21
17
/AD23
Address/Data 23
18
/AD25
Address/Data 25
19
/AD27
Address/Data 27
20
/AD29
Address/Data 29
21
/AD31
Address/Data 31
22
GND
Ground
23
GND
Ground
24
/ARB1
25
/ARB3
26
/ID1
27
/ID3
28
/ACK
29
+5 V
+5 VDC
30
/RQST
31
/NMRQ
32
+12 V
+12 VDC
Row B
Pin
Name
Description
1
-12 V
-12 VDC
2
GND
Ground
3
GND
Ground
4
+5 V
+5 VDC
5
+5 V
+5 VDC
6
+5 V
+5 VDC
7
+5 V
+5 VDC
8
*
Reserved ?
9
*
Reserved ?
10
*
Reserved ?
11
*
Reserved ?
12
GND
Ground
13
GND
Ground
14
GND
Ground
15
GND
Ground
16
GND
Ground
17
GND
Ground
18
GND
Ground
19
GND
Ground
20
GND
Ground
21
GND
Ground
22
GND
Ground
23
GND
Ground
24
**
Reserved ?
25
**
Reserved ?
26
**
Reserved ?
27
**
Reserved ?
28
+5 V
+5 VDC
29
+5 V
+5 VDC
30
GND
Ground
31
GND
Ground
32
+12 V
Row C
Pin
Name
Description
1
/RESET
Reset
2
-
3
+5 V
+5 VDC
4
+5 V
+5 VDC
5
/TM0
6
/AD0
Address/Data 0
7
/AD2
Address/Data 2
8
/AD4
Address/Data 4
9
/AD6
Address/Data 6
10
/AD8
Address/Data 8
11
/AD10
Address/Data 10
12
/AD12
Address/Data 12
13
/AD14
Address/Data 14
14
/AD16
Address/Data 16
15
/AD18
Address/Data 18
16
/AD20
Address/Data 20
17
/AD22
Address/Data 22
18
/AD24
Address/Data 24
19
/AD26
Address/Data 26
20
/AD28
Address/Data 28
21
/AD30
Address/Data 30
22
GND
Ground
23
/PFW
24
/ARB0
25
/ARB2
26
/ID0
27
/ID2
28
/START
29
+5 V
+5 VDC
30
+5 V
+5 VDC
31
GND
Ground
32
/CLK
Clock
Notes
The physical connector is a 96-pin DIN 41612 (Euro-DIN / IEC 60603-2) three-row connector, 32 pins per row (A, B, C) on a 2.54 mm (0.1 inch) pitch. The card edge carries the male plug; the backplane (computer side) carries the female receptacle.
Row B is the power and ground plane row in standard NuBus: pins B1 and B32 carry ±12 V, pins B4–B7 and B28–B29 carry +5 V, and pins B2–B3 and B12–B23 and B30–B31 are ground. NuBus-90 later repurposed Row B pins 8–11 and 24–27 for new control signals.
Pins A2 and C2 are reserved no-connect in standard NuBus (IEEE 1196). The NuBus-90 proposal re-designates A2 as SB0 and C2 as SB1, forming a high-speed serial bus. Their listing as ‘-’ in the pin table is correct for IEEE 1196.
Row B pins marked * (B8–B11) and ** (B24–B27) are reserved in standard NuBus. NuBus-90 assigns /TM2 (B8), /CM0 (B9), /CM1 (B10), /CM2 (B11) to the * group and /CLK2X (B24), STDBYPWR (B25), /CLK2XEN (B26), /CBUSY (B27) to the ** group.
The bus clock (/CLK, Row C pin 32) runs at 10 MHz for standard NuBus. NuBus-90 adds /CLK2X at 20 MHz for card-to-card double-rate block transfers (~70 MB/s burst).
Slot IDs are carried on the four /ID lines (ID0–ID3), enabling cards to self-identify during system startup without DIP switches or jumpers.
Standard NuBus cards are backward compatible with NuBus-90 slots; a 10 MHz card operates normally in a Quadra backplane.
Signals
/AD0–/AD31 — 32 multiplexed address/data lines; active-low, shared by all bus masters and targets. Address and data are time-multiplexed on the same lines.
/CLK — 10 MHz synchronous bus clock; all NuBus transactions are clocked relative to this signal.
/RESET — System reset; asserted by the bus master (host) to initialise all cards.
/START — Indicates the start of a bus transaction; driven by the current bus master.
/ACK — Acknowledge; driven by the addressed slave to confirm receipt of a transaction.
/TM0, /TM1 — Transaction mode bits; together they encode the type and size of the current bus cycle (e.g. read, write, block transfer).
/ARB0–/ARB3 — Four-wire fair arbitration lines; each potential bus master drives and monitors these lines to win bus mastership without a central arbiter.
/RQST — Bus request; asserted by a card to request mastership of the bus.
/NMRQ — Non-master request; used by cards that never act as bus master to signal attention to the host.
/ID0–/ID3 — Slot-ID lines; hard-wired per slot on the backplane so each card can determine its own slot address at startup. Standard NuBus address space per slot: $FA000000–$FDFFFFFF; super-slot space: $A0000000–$DFFFFFFF.
/SPV — Supervisor address; distinguishes supervisor-mode from user-mode accesses.
/SP — Supervisor parity; provides parity protection for supervisor-mode transfers.
/PFW — Power-fail warning; asserted by the power supply to alert cards of an impending power failure, allowing orderly shutdown.
+5 V, +12 V, -12 V — DC power rails distributed across all three connector rows.
GND — Signal and power ground; heavily distributed across rows A, B, and C for low-impedance returns.
A2 (-) — Reserved no-connect in IEEE 1196 NuBus; re-designated SB0 (serial bus 0) in the NuBus-90 proposal.
C2 (-) — Reserved no-connect in IEEE 1196 NuBus; re-designated SB1 (serial bus 1) in the NuBus-90 proposal.