Communication and Networking Riser (CNR)

The Communication and Networking Riser (CNR) is an Intel-defined riser-card slot introduced in February 2000 (specification v1.0) for ATX, microATX, and FlexATX motherboards, intended to reduce the OEM cost of integrating audio, modem, and networking functions. The slot uses a physically keyed 60-pin edge connector — preventing inadvertent insertion of ISA or PCI cards — and exists in two keyed variants: Type A (carrying an 8-pin PHY LAN interface aimed at Power Line Communication devices) and Type B (carrying a 17-pin MII interface per IEEE 802.3u for standard 10/100 Ethernet PHYs). CNR v1.1, released October 2000, extended support to USB 2.0 alongside USB 1.x. The slot was never widely adopted outside Intel-chipset platforms and was discontinued within a few years of its introduction.

CNR slot (on the PC mainboard).

Type A CNR connector

Type B CNR connector

Notes

The CNR slot is physically keyed to prevent insertion of ISA or PCI cards. Two keying variants exist: Type A accepts cards with an 8-pin PHY LAN interface (Power Line Communication); Type B accepts cards with a 17-pin MII interface (IEEE 802.3u, standard 10/100 Ethernet). The two variants are not interchangeable. Both full-height and low-profile I/O bracket configurations are defined in the specification. All CNR cards are required to carry a Plug-and-Play Microwire EEPROM (accessed via EE_DIN/EE_DOUT/EE_CS/EE_SHCLK) and an SMBus EEPROM for system management. The +5Vdual and +3.3Vdual supply rails carry both main and standby power and must not be shorted to the corresponding main-only rails (+5VD, +3.3VD), as doing so would disable deep-sleep wake capability. The AC97_BITCLK nominal frequency is 12.288 MHz.

Signals

Signals common to both Type A and Type B connectors:

• GND — power supply and signal ground return.
• +5VD — +5 V main digital power supply.
• +3.3VD — +3.3 V main digital power supply.
• +5Vdual — +5 V main/standby supply; provides full power in active state and limited power during sleep; used also for USB bus power.
• +3.3Vdual — +3.3 V main/standby supply; provides full power in active state and limited power during sleep.
• +12V — +12 V main power supply.
• -12V — −12 V main power supply.
• USB+ — positive side of the differential USB 1.x/2.0 data pair.
• USB- — negative side of the differential USB 1.x/2.0 data pair.
• USB_OC# — active-low USB over-current signal from the CNR card to the host.
• EE_DIN — serial data from the host MAC Microwire interface to the Microwire EEPROM on the CNR card.
• EE_DOUT — serial data from the Microwire EEPROM on the CNR card to the host MAC Microwire interface.
• EE_CS — chip-select for the Microwire EEPROM; active high; low at reset.
• EE_SHCLK — serial clock from the host MAC Microwire interface to the Microwire EEPROM.
• SMB_A0 — bit 0 (LSB) of the 3-bit SMBus EEPROM address for the CNR card.
• SMB_A1 — bit 1 of the 3-bit SMBus EEPROM address for the CNR card.
• SMB_A2 — bit 2 (MSB) of the 3-bit SMBus EEPROM address for the CNR card.
• SMB_SDA — bidirectional SMBus serial data between host SMBus master and CNR slave devices.
• SMB_SCL — SMBus serial clock from host SMBus master to CNR slave devices.
• AC97_RESET# — active-low reset for the AC'97 link.
• AC97_SYNC — 1.3 µs synchronisation pulse from AC'97 controller to all codecs on the link.
• AC97_SDATA_OUT — serial data from the AC'97 controller to all codecs on the link.
• AC97_SDATA_IN0 — serial data from the primary AC'97 codec to the controller.
• AC97_SDATA_IN1 — serial data from a primary or secondary AC'97 codec to the controller.
• AC97_BITCLK — 12.288 MHz serial clock from the primary codec to the AC'97 controller and non-primary codecs; direction reverses when the CNR holds primary codec role.
• CDC_DN_ENAB# — codec-down enable; low indicates the motherboard’s primary codec is active and the CNR demotes its codecs; high indicates a CNR codec is taking primary control and the motherboard disables its codecs.

Type A-specific signals (8-pin PHY/PLC LAN interface):

• LAN_TXD0 — bit 0 (LSB) of the 3-bit MAC-to-PLC transmit data bus.
• LAN_TXD1 — bit 1 of the 3-bit MAC-to-PLC transmit data bus.
• LAN_TXD2 — bit 2 (MSB) of the 3-bit MAC-to-PLC transmit data bus.
• LAN_RXD0 — bit 0 (LSB) of the 3-bit PLC-to-MAC receive data bus.
• LAN_RXD1 — bit 1 of the 3-bit PLC-to-MAC receive data bus.
• LAN_RXD2 — bit 2 (MSB) of the 3-bit PLC-to-MAC receive data bus.
• LAN_CLK — data clock from the PLC to the MAC; frequency determines the PLC-to-MAC transfer rate.
• LAN_RSTSYNC — dual-function signal providing either a reset pulse or a synchronisation pulse from the MAC to the PLC.

Type B-specific signals (17-pin MII interface, IEEE 802.3u):

• MII_MDC — management data clock from the Management Data Controller to the MII PHY.
• MII_MDIO — bidirectional management data for PHY control and status registers.
• MII_CRS — carrier sense from the PHY to the MAC; asserted when the medium is active.
• MII_COL — collision detect from the PHY to the MAC; asserted on a collision.
• MII_TXC — transmit clock from the MAC to the PHY.
• MII_RXC — receive clock from the PHY to the MAC.
• MII_TXEN — transmit enable from the MAC; indicates that MII_TXD[3:0] data may be placed on the wire.
• MII_TXD0 — bit 0 (LSB) of the 4-bit MAC-to-PHY transmit data bus.
• MII_TXD1 — bit 1 of the 4-bit MAC-to-PHY transmit data bus.
• MII_TXD2 — bit 2 of the 4-bit MAC-to-PHY transmit data bus.
• MII_TXD3 — bit 3 (MSB) of the 4-bit MAC-to-PHY transmit data bus.
• MII_RXDV — receive data valid from the PHY; indicates that MII_RXD[3:0] carries valid data.
• MII_RXERR — receive error from the PHY; asserted when an error is detected during frame reception.
• MII_RXD0 — bit 0 (LSB) of the 4-bit PHY-to-MAC receive data bus.
• MII_RXD1 — bit 1 of the 4-bit PHY-to-MAC receive data bus.
• MII_RXD2 — bit 2 of the 4-bit PHY-to-MAC receive data bus.
• MII_RXD3 — bit 3 (MSB) of the 4-bit PHY-to-MAC receive data bus.

References

• Communication and Networking Riser (CNR) Specification — Intel Corporation (hosted by ALSA Project)

Category:Buses Connectors