PCI

PCI = Peripheral Component Interconnect

The Peripheral Component Interconnect (PCI) is a synchronous local bus developed by Intel and standardised by the PCI Special Interest Group (PCI-SIG). From the early 1990s to the mid-2000s it was the dominant PC expansion bus, displacing ISA, EISA, MCA and VESA Local Bus, before being succeeded in turn by PCI Express. A 32-bit bus running at up to 33 MHz reaches a peak transfer rate of 132 MB/s; the 64-bit and 66 MHz variants reach 264 MB/s, and a 64-bit, 66 MHz bus reaches 528 MB/s. To keep the pin count down, address and data share the same lines (the multiplexed AD bus), and the bus uses reflected-wave rather than incident-wave switching.

This page is an overview for designers and hobbyists rather than a complete account of the standard: I/O operations are described in the most detail, while memory operations — which an I/O card rarely handles — are only outlined. Because of the higher clock speeds involved, PCI cards are harder to design than ISA cards. Several vendors offer PCI prototyping cards, and FPGA suppliers such as Xilinx provide PCI-compliant cores that can serve as a starting point for a design.

    PCI Universal Card 32/64 bit 
      ---------------------------------------------------------------- 
     |    PCI         Component Side (side B)                         | 
     |                                                                | 
     |                                                                | 
     |                                                optional        | 
     |    ____     mandatory 32-bit pins            64-bit pins  _____| 
     |___|    |||||||--|||||||||||||||||--|||||||--|||||||||||||| 
              ^     ^  ^               ^  ^     ^  ^            ^ 
            b01   b11  b14           b49  b52 b62  b63          b94 

    PCI 5V Card 32/64 bit 
     |                                                optional        | 
     |    ____     mandatory 32-bit pins            64-bit pins  _____| 
     |___|    ||||||||||||||||||||||||||--|||||||--|||||||||||||| 

    PCI 3.3V Card 32/64 bit 
     |                                                optional        | 
     |    ____     mandatory 32-bit pins            64-bit pins  _____| 
     |___|    |||||||--||||||||||||||||||||||||||--|||||||||||||| 

98+22 PIN EDGE CONNECTOR at the computer.

Notes

• Pins 63-94 exist only on 64-bit PCI implementations; the 64-bit extension carries AD[63:32], C/BE[7:4]# and PAR64. REQ64#/ACK64# sit at position 60 in the 32-bit section so 32-bit slots can leave them open.
• +V I/O is 3.3 V on 3.3 V boards and 5 V on 5 V boards; on the Universal board these pins define the signalling rail that the board’s I/O buffers adapt to.
• Keying and voltage. The standard defines a 5 V and a 3.3 V signalling connector, and three card types: a 5 V card (notch at positions 50/51), a 3.3 V card (notch at positions 12/13), and a Universal card with both notches, which is why it fits either slot.
• Present detect. PRSNT1#/PRSNT2# indicate that a board is fitted and its maximum power draw: both open = no board; PRSNT1# to ground = 25 W; PRSNT2# to ground = 15 W; both to ground = 7.5 W.
• M66EN (pin B49) signals a 66 MHz-capable board; it is treated as ground in a 33 MHz environment.
• Boards that do not implement JTAG boundary scan must connect TDI to TDO so the scan chain is not broken.

Signal Descriptions:

• AD(x): Address/Data Lines.
• CLK: Clock. 33 MHz maximum.
• C/BE(x): Command, Byte Enable.
• FRAME: Used to indicate whether the cycle is an address phase or a data phase.
• DEVSEL: Device Select.
• IDSEL: Initialization Device Select
• INT(x): Interrupt
• IRDY: Initiator Ready
• LOCK: Used to manage resource locks on the PCI bus.
• REQ: Request. Requests a PCI transfer.
• GNT: Grant. indicates that permission to use PCI is granted.
• PAR: Parity. Used for AD0-31 and C/BE0-3.
• PERR: Parity Error.
• RST: Reset.
• SBO: Snoop Backoff.
• SDONE: Snoop Done.
• SERR: System Error. Indicates an address parity error for special cycles or a system error.
• STOP: Asserted by Target. Requests the master to stop the current transfer cycle.
• TCK: Test Clock
• TDI: Test Data Input
• TDO: Test Data Output
• TMS: Test Mode Select
• TRDY: Target Ready
• TRST: Test Logic Reset
• M66EN: 66 MHz Enable. Indicates a 66 MHz-capable board; tied to ground for 33 MHz operation.
• REQ64: Request 64-bit transfer (asserted by the master).
• ACK64: Acknowledge 64-bit transfer (asserted by the target that supports it).
• PAR64: Parity for the upper AD[63:32] and C/BE[7:4]# lines.

The PCI bus treats all transfers as a burst operation. Each cycle begins with an address phase followed by one or more data phases. Data phases may repeat indefinitely, but are limited by a timer that defines the maximum amount of time that the PCI device may control the bus. This timer is set by the CPU as part of the configuration space. Each device has its own timer (see the Latency Timer in the configuration space).

The same lines are used for address and data. The command lines are also used for byte enable lines. This is done to reduce the overall number of pins on the PCI connector.

The Command lines (C/BE3 to C/BE0) indicate the type of bus transfer during the address phase.

The three basic types of transfers are I/O, Memory, and Configuration.

PCI transfers are synchronous to the rising edge of CLK. A cycle begins when the initiator asserts FRAME and drives the command and address; one or more data phases follow, and either the initiator (via IRDY) or the target (via TRDY) may insert wait states until both are ready. See the PCI Local Bus Specification for the detailed cycle timing.

References

• PCI Local Bus Specification, Revision 2.1 (PCI-SIG, June 1995) — connector pinout (Table 4-11), present-detect definitions and keying.
• PCI Local Bus Specification, Revision 2.2 (PCI-SIG, December 1998) — Internet Archive scan of the later revision.
• PCI bus technical notes and signal descriptions: Mark Sokos.

Category:Buses Connectors