The Commodore CD32 expansion port is a 182-pin connector sharing the same physical form factor as the IBM Micro Channel Architecture (MCA) connector. Introduced with the CD32 games console in 1993, it exposes the full AGA chipset bus — the same architecture used in the Amiga 1200 and Amiga 4000 — along with RGB analogue video taken directly from the digital-to-analogue converter outputs, digital audio input for mixing external MPEG or FMV audio with the CD audio and Amiga audio streams, and genlock signals. The port was designed primarily to accept the Full Motion Video (FMV) MPEG cartridge and SX-1/SX-32 type expansion units that added a keyboard, floppy drive, IDE interface, and serial/parallel ports to the otherwise console-only machine.
182 PIN CONNECTOR (SAME AS MCA) at the computer
| Pin | Name | Description | Comment |
|---|---|---|---|
| 1 | A31 | Address 31 | Probably not connected since 68EC020 |
| 2 | A30 | Address 30 | Probably not connected since 68EC020 |
| 3 | A29 | Address 29 | Probably not connected since 68EC020 |
| 4 | A28 | Address 28 | Probably not connected since 68EC020 |
| 5 | A27 | Address 27 | Probably not connected since 68EC020 |
| 6 | A26 | Address 26 | Probably not connected since 68EC020 |
| 7 | A25 | Address 25 | Probably not connected since 68EC020 |
| 8 | A24 | Address 24 | |
| 9 | DGND | Data Ground | |
| 10 | VCC | +5 VDC | |
| 11 | A23 | Address 23 | |
| 12 | A22 | Address 22 | |
| 13 | A21 | Address 21 | |
| 14 | A20 | Address 20 | |
| 15 | A19 | Address 19 | |
| 16 | A18 | Address 18 | |
| 17 | A17 | Address 17 | |
| 18 | A16 | Address 16 | |
| 19 | DGND | Data Ground | |
| 20 | VCC | +5 VDC | |
| 21 | A15 | Address 15 | |
| 22 | A14 | Address 14 | |
| 23 | A13 | Address 13 | |
| 24 | A12 | Address 12 | |
| 25 | A11 | Address 11 | |
| 26 | A10 | Address 10 | |
| 27 | A9 | Address 9 | |
| 28 | A8 | Address 8 | |
| 29 | DGND | Data Ground | |
| 30 | VCC | +5 VDC | |
| 31 | A7 | Address 7 | |
| 32 | A6 | Address 6 | |
| 33 | A5 | Address 5 | |
| 34 | A4 | Address 4 | |
| 35 | A3 | Address 3 | |
| 36 | A2 | Address 2 | |
| 37 | A1 | Address 1 | |
| 38 | A0 | Address 0 | |
| 39 | DGND | Data Ground | |
| 40 | VCC | +5 VDC | |
| 41 | D31 | Data 31 | |
| 42 | D30 | Data 30 | |
| 43 | D29 | Data 29 | |
| 44 | D28 | Data 28 | |
| 45 | D27 | Data 27 | |
| 46 | D26 | Data 26 | |
| 47 | D25 | Data 25 | |
| 48 | D24 | Data 24 | |
| 49 | DGND | Data Ground | |
| 50 | VCC | +5 VDC | |
| 51 | D23 | Data 23 | |
| 52 | D22 | Data 22 | |
| 53 | D21 | Data 21 | |
| 54 | D20 | Data 20 | |
| 55 | D19 | Data 19 | |
| 56 | D18 | Data 18 | |
| 57 | D17 | Data 17 | |
| 58 | D16 | Data 16 | |
| 59 | DGND | Data Ground | |
| 60 | VCC | +5 VDC | |
| 61 | D15 | Data 15 | |
| 62 | D14 | Data 14 | |
| 63 | D13 | Data 13 | |
| 64 | D12 | Data 12 | |
| 65 | D11 | Data 11 | |
| 66 | D10 | Data 10 | |
| 67 | D9 | Data 9 | |
| 68 | D8 | Data 8 | |
| 69 | DGND | Data Ground | |
| 70 | VCC | +5 VDC | |
| 71 | D7 | Data 7 | |
| 72 | D6 | Data 6 | |
| 73 | D5 | Data 5 | |
| 74 | D4 | Data 4 | |
| 75 | D3 | Data 3 | |
| 76 | D2 | Data 2 | |
| 77 | D1 | Data 1 | |
| 78 | D0 | Data 0 | |
| 79 | DGND | Data Ground | |
| 80 | VCC | +5 VDC | |
| 81 | /IPL2 | Interrupt Priority Level 2 | |
| 82 | /IPL1 | Interrupt Priority Level 1 | |
| 83 | /IPL0 | Interrupt Priority Level 0 | |
| 84 | |||
| 85 | /RST | Reset | |
| 86 | /HALT | Halt | |
| 87 | /ECS | ECS?? | |
| 88 | /OCS | OCS?? | |
| 89 | SIZE1 | Size 1 | Indicates number of bytes remaining to transfer |
| 90 | SIZE0 | Size 0 | Indicates number of bytes remaining to transfer |
| 91 | /AS | Address Strobe | |
| 92 | /DS | Data Strobe | |
| 93 | /R/W | Read/Write | |
| 94 | /BERR | Bus Error | |
| 95 | |||
| 96 | /AVEC | Autovector Req | Autovector request during interrupt acknowledge |
| 97 | /DSACK1 | Data Ack 1 | Data transfer and size acknowledge |
| 98 | /DSACK0 | Data Ack 0 | Data transfer and size acknowledge |
| 99 | CPUCLK_A | ||
| 100 | |||
| 101 | DGND | Data Ground | |
| 102 | VCC | +5 VDC | |
| 103 | FC2 | Function Codes 2 | |
| 104 | FC1 | Function Codes 1 | |
| 105 | FC0 | Function Codes 0 | |
| 106 | |||
| 107 | |||
| 108 | |||
| 109 | |||
| 110 | |||
| 111 | /CPU_BR | CPU bus request?? | |
| 112 | /EXP_BG | Expansion bus granted?? | |
| 113 | /CPU_BG | CPU bus granted?? | |
| 114 | /EXP_BR | Expansion bus request?? | |
| 115 | |||
| 116 | |||
| 117 | /PUNT | ||
| 118 | /RESET | 68020 RESET | |
| 119 | /INT2 | Interrupt 2 | Generate a level 2 interrupt |
| 120 | /INT6 | Interrupt 2 | Generate a level 6 interrupt |
| 121 | /KB_CLOCK | Keyboard clock | |
| 122 | /KB_DATA | Keyboard data | |
| 123 | /FIRE0 | Fire Button 0?? | |
| 124 | /FIRE1 | Fire Button 1?? | |
| 125 | /LED | Power On LED ?? | |
| 126 | /ACTIVE | Disk active LED | |
| 127 | /RXD | Serial Receive | Serial data in |
| 128 | /TXD | Serial Transmit | Serial data out |
| 129 | /DKRD | Floppy interface (Paula?) | |
| 130 | /DKWD | Floppy interface (Paula?) | |
| 131 | SYSTEM | ||
| 132 | /DKWE | Floppy interface (Paula?) | |
| 133 | CONFIG_OUT | ||
| 134 | |||
| 135 | DGND | Data Ground | |
| 136 | +12V | +12V DC | |
| 137 | DGND | Data Ground | |
| 138 | +12V | +12V DC | |
| 139 | 17MHZ | For FMV interface ?? | |
| 140 | EXT_AUDIO | For FMV interface ?? | |
| 141 | DA_DATA | For FMV interface ?? | |
| 142 | /MUTE | For FMV interface ?? | |
| 143 | DA_LRCLK | For FMV interface ?? | |
| 144 | DA_BCLK | For FMV interface ?? | |
| 145 | DGND | Data Ground | |
| 146 | VCC | +5 VDC | |
| 147 | DR | Digital Red | |
| 148 | DG | Digital Green | |
| 149 | DB | Digital Blue | |
| 150 | DI | Digital Intensity | |
| 151 | /PIXELSW_EXT | ||
| 152 | /PIXELSW | ||
| 153 | /BLANK | ||
| 154 | PIXELCLK | Pixelclock | For manipulating RBG data |
| 155 | DGND | Data Ground | |
| 156 | VCC | +5 VDC | |
| 157 | /CSYNC | Composite sync | Not buffered. |
| 158 | CCK_B | Color clock ?? | |
| 159 | /HSYNC | Horizontal sync | |
| 160 | /VSYNC | Vertical sync | |
| 161 | VGND | Video ground | |
| 162 | VGND | Video ground | |
| 163 | AR_EXT | Analog Red External | |
| 164 | AR | Analog Red | |
| 165 | AG_EXT | Analog Green External | |
| 166 | AG | Analog Green | |
| 167 | AB_EXT | Analog Blue External | |
| 168 | AB | Analog Blue | |
| 169 | VGND | Video ground | |
| 170 | VGND | Video ground | |
| 171 | /NTSC | ||
| 172 | /XCLKEN | Enable External video clock | (Genlock) |
| 173 | XCLK | External video clock | (Genlock) |
| 174 | /EXT_VIDEO | External Video | Disable internal video interfaces |
| 175 | DGND | Data Ground | |
| 176 | VCC | +5 VDC | |
| 177 | AGND | Audio Ground | |
| 178 | +12V | +12V DC | |
| 179 | LEFT_EXT | Left sound External | |
| 180 | LEFT | Left sound | |
| 181 | RIGHT_EXT | Right sound External | |
| 182 | RIGHT | Right sound |
Notes
The connector is mechanically identical to the IBM MCA (Micro Channel Architecture) edge connector at 182 pins, though the signal assignments are entirely Commodore-specific. The CD32 uses a 68EC020 processor running at approximately 14 MHz; address lines A31–A24 are present on the connector but are not driven by the 68EC020 (which has only a 24-bit physical address bus) and are most likely unconnected. All logic signals are 5 V TTL-compatible. Power rails available are +5 V (multiple pins) and +12 V; expansion units must not exceed the current budget of the CD32’s internal supply. The RGB analogue video signals (AR, AG, AB and their _EXT counterparts) are taken directly from the AGA DAC outputs and are not buffered at the connector, so expansion units performing genlock or overlay operations must provide their own signal conditioning.
Signals
- A31–A0 — 32-bit address bus from the 68EC020; A31–A24 are likely unconnected internally due to the EC020’s 24-bit physical address limit
- D31–D0 — 32-bit data bus
- DGND — digital ground reference for bus signals
- VCC — +5 V DC supply for expansion logic
- /IPL2, /IPL1, /IPL0 — active-low interrupt priority level inputs to the 68EC020, encoding the current interrupt level
- /RST — system reset signal
- /HALT — processor halt signal
- /ECS, /OCS — chipset compatibility identification signals (Enhanced Chip Set / Original Chip Set select lines; exact function on AGA CD32 uncertain)
- SIZE1, SIZE0 — indicate the number of bytes remaining to be transferred in the current bus cycle (68020 dynamic bus sizing)
- /AS — address strobe; asserted when the address bus contains a valid address
- /DS — data strobe; asserted when the data bus is valid (write) or to request data (read)
- /R/W — read/write direction line; high = read, low = write
- /BERR — bus error; asserted to signal an error condition on the current bus cycle
- /AVEC — autovector request; asserted during interrupt acknowledge to request an autovector rather than an externally supplied vector
- /DSACK1, /DSACK0 — data transfer and size acknowledge lines used by the 68020 for dynamic bus sizing and to terminate a bus cycle
- CPUCLK_A — CPU clock signal (approximately 14 MHz)
- FC2, FC1, FC0 — function code outputs from the 68EC020 indicating the address space type of the current bus cycle
- /CPU_BR — CPU bus request; used by an expansion device to request mastership of the local bus
- /EXP_BG — expansion bus grant; asserted by the CPU to grant bus mastership to a requesting expansion device
- /CPU_BG — CPU bus grant output
- /EXP_BR — expansion bus request; alternate bus request line for expansion devices
- /PUNT — signal allowing an expansion device to pass a bus cycle back to the on-board logic
- /RESET — 68020 RESET instruction output; can be used to reset peripherals
- /INT2 — generates a level 2 interrupt to the processor
- /INT6 — generates a level 6 interrupt to the processor
- /KB_CLOCK — keyboard clock line (used by SX-1/SX-32 type keyboard expansion units)
- /KB_DATA — keyboard data line
- /FIRE0, /FIRE1 — joystick fire button inputs (exact routing uncertain)
- /LED — power-on LED control (exact function uncertain)
- /ACTIVE — floppy/disk activity LED
- /RXD — serial receive data input
- /TXD — serial transmit data output
- /DKRD — floppy read data (Paula chip interface)
- /DKWD — floppy write data (Paula chip interface)
- SYSTEM — system signal (function not fully documented)
- /DKWE — floppy write enable (Paula chip interface)
- CONFIG_OUT — AutoConfig daisy-chain output; allows self-configuring expansion cards to be sequentially mapped into the Amiga address space during boot
- +12V — +12 V DC supply
- 17MHZ — 17 MHz clock, provided for the FMV (Full Motion Video) MPEG module interface
- EXT_AUDIO — external audio input for mixing MPEG/FMV audio with the CD and Amiga audio streams
- DA_DATA — digital audio serial data (I²S-style interface for FMV audio)
- /MUTE — audio mute control (FMV interface)
- DA_LRCLK — digital audio left/right word clock (FMV interface)
- DA_BCLK — digital audio bit clock (FMV interface)
- DR, DG, DB — digital red, green, blue video signals from the AGA chipset
- DI — digital intensity/brightness signal
- /PIXELSW_EXT — external pixel switch input (genlock/overlay use)
- /PIXELSW — pixel switch output
- /BLANK — composite blank signal
- PIXELCLK — pixel clock for synchronising manipulation of the RGB data stream
- /CSYNC — composite sync output; not buffered at the connector
- CCK_B — colour clock (3.58 MHz NTSC or PAL equivalent)
- /HSYNC — horizontal sync
- /VSYNC — vertical sync
- VGND — video ground reference for analogue video signals
- AR_EXT, AG_EXT, AB_EXT — external analogue red, green, blue inputs for genlock overlay mixing
- AR, AG, AB — analogue red, green, blue outputs from the AGA DAC; taken directly from the converter leads
- /NTSC — NTSC/PAL mode identifier signal
- /XCLKEN — enable external video clock input (genlock)
- XCLK — external video clock input (genlock reference)
- /EXT_VIDEO — when asserted, disables the CD32’s internal video output interfaces
- AGND — audio ground reference
- LEFT_EXT, RIGHT_EXT — external left and right analogue audio inputs for mixing
- LEFT, RIGHT — left and right analogue audio outputs
References
- CD32 Developer Notes, Revision 3 — Commodore Amiga, Inc., August 1993
- Amiga Hardware Reference Manual, 3rd Edition — Commodore-Amiga Inc., 1991