ISA

ISA = Industry Standard Architecture

The ISA bus is the expansion bus introduced with the original IBM PC/XT in 1981 as an 8-bit interface and extended to 16 bits with the IBM PC/AT in 1984; the two versions are commonly called the XT bus and the AT bus. The AT bus is upwardly compatible, so cards designed for the 8-bit XT bus also work in 16-bit AT slots. The bus ran for years as a de-facto standard: the name “Industry Standard Architecture” was coined later by PC-clone makers, and an IEEE effort to formalise it (the P996 draft) never progressed past draft status. A 32-bit extension, EISA (Extended ISA), was introduced in 1988 but is not detailed here. ISA was eventually superseded by the VESA Local Bus and then by PCI.

This page is a practical reference rather than a complete specification — enough information for designers and hobbyists to work with XT- and AT-compatible cards.

Physical Design:

ISA cards can be either 8-bit or 16-bit. 8-bit cards only uses the first 62 pins and 16-bit cards uses all 98 pins. Some 8-bit cards uses some of the 16-bit extension pins to get more interrupts.

8-bit card:

62 Pin Connector at the card

62 Pin Connector at the computer

16-bit card:

62+36 PIN EDGE CONNECTOR MALE at the card

. 62+36 PIN EDGE CONNECTOR FEMALE at the computer

Signal Descriptions:

• +5, -5, +12, -12: Power supplies. -5 is often not implemented.
• AEN: Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O device from responding to the I/O command lines during a DMA transfer. When AEN is active, the DMA Controller has control of the address bus as the memory and I/O read/write command lines.
• BALE: Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle. Memory devices should latch the LA bus on the falling edge of BALE. Some references refer to this signal as Buffered Address Latch Enable, or just Address Latch Enable (ALE). The Buffered-Address Latch Enable is used to latch SA0-19 on the falling edge. This signal is forced high during DMA cycles.
• BCLK: Bus Clock, 33% Duty Cycle. Frequency Varies. 4.77 to 8 MHz typical. 8.3 MHz is specified as the maximum, but many systems allow this clock to be set to 12 MHz and higher.
• DACKx: DMA Acknowledge. The active-low DMA Acknowledge 0 to 3 and 5 to 7 are the corresponding acknowledge signals for DRQ 0-3, 5-7.
• DRQx: DMA Request. These signals are asynchronous channel requests used by I/O channel devices to gain DMA service. DMA request channels 0-3 are for 8-bit data transfer. DAM request channels 5-7 are for 16-bit data transfer. DMA request channel 4 is used internally on the system board. DMA requests should be held high until the corresponding DACK line goes active. DMA requests are serviced in the following priority sequence: High: DRQ 0, 1, 2, 3, 5, 6, 7 Lowest
• IOCS16: I/O size 16. Generated by a 16 bit slave when addressed by a bus master. The active-low I/O Chip Select 16 indicates that the current transfer is a 1 wait state, 16 bit I/O cycle. Open Collector.
• I/O CH CK: Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC, externally to the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach the cpu. The I/O Channel Check is an active-low signal which indicates that a parity error exists in a device on the I/O channel.
• I/O CH RDY: Channel Ready. Setting this low prevents the default ready timer from timing out. The slave device may then set it high again when it is ready to end the bus cycle. Holding this line low for too long (15 microseconds, typical) can prevent RAM refresh cycles on some systems. This signal is called IOCHRDY (I/O Channel Ready) by some references. CHRDY and NOWS should not be used simultaneously. This may cause problems with some bus controllers. This signal is pulled low by a memory or I/O device to lengthen memory or I/O read/write cycles. It should only be held low for a minimum of 2.5 microseconds.
• IOR: The I/O Read is an active-low signal which instructs the I/O device to drive its data onto the data bus, SD0-SD15.
• IOW: The I/O Write is an active-low signal which instructs the I/O device to read data from the data bus, SD0-SD15.
• IRQx: Interrupt Request. IRQ2 has the highest priority. IRQ 10-15 are only available on AT machines, and are higher priority than IRQ 3-7. The Interrupt Request signals which indicate I/O service attention. They are prioritized in the following sequence: Highest IRQ 9(2),10,11,12,14,3,4,5,6,7
• LAxx: Latchable Address lines. Combine with the lower address lines to form a 24 bit address space (16 MB) These unlatched address signals give the system up to 16 MB of address ability. The are valid when “BALE” is high.
• MASTER: 16 bit bus master. Generated by the ISA bus master when initiating a bus cycle. This active-low signal is used in conjunction with a DRQ line by a processor on the I/O channel to gain control of the system. The I/O processor first issues a DRQ, and upon receiving the corresponding DACK, the I/O processor may assert MASTER, which will allow it to control the system address, data and control lines. This signal should not be asserted for more than 15 microseconds, or system memory may be corrupted du to the lack of memory refresh activity.
• MEMCS16: The active-low Memory Chip Select 16 indicates that the current data transfer is a 1 wait state, 16 bit data memory cycle.
• MEMR: The Memory Read is an active-low signal which instructs memory devices to drive data onto the data bus SD0-SD15. This signal is active on all memory read cycles.
• MEMW: The Memory Write is an active-low signal which instructs memory devices to store data present on the data bus SD0-SD15. This signal is active on all memory write cycles.
• NOWS: No Wait State. Used to shorten the number of wait states generated by the default ready timer. This causes the bus cycle to end more quickly, since wait states will not be inserted. Most systems will ignore NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers, and both signals should not be active simultaneously.
• OSC: Oscillator, 14.31818 MHz, 50% Duty Cycle. Frequency varies. This was originally divided by 3 to provide the 4.77 MHz cpu clock of early PCs, and divided by 12 to produce the 1.19 MHz system clock. Some references have placed this signal as low as 1 MHz (possibly referencing the system clock), but most modern systems use 14.318 MHz. This frequency (14.318 MHz) is four times the television colorburst frequency. Refresh timing on many PC’s is based on OSC/18, or approximately one refresh cycle every 15 microseconds. Many modern motherboards allow this rate to be changed, which frees up some bus cycles for use by software, but also can cause memory errors if the system RAM cannot handle the slower refresh rates.
• REFRESH: Refresh. Generated when the refresh logic is bus master. This active-low signal is used to indicate a memory refresh cycle is in progress. An ISA device acting as bus master may also use this signal to initiate a refresh cycle.
• RESET: This signal goes low when the machine is powered up. Driving it low will force a system reset. This signal goes high to reset the system during powerup, low line-voltage or hardware reset.
• SA0-SA19: System Address Lines, tri-state. The System Address lines run from bit 0 to bit 19. They are latched on to the falling edge of “BALE”.
• SBHE: System Bus High Enable, tristate. Indicates a 16 bit data transfer. The System Bus High Enable indicates high byte transfer is occurring on the data bus SD8-SD15. This may also indicate an 8 bit transfer using the upper half of the bus data (if an odd address is present).
• SD0-SD16: System Data lines, or Standard Data Lines. They are bidrectional and tri-state. On most systems, the data lines float high when not driven. These 16 lines provide for data transfer between the processor, memory and I/O devices.
• SMEMR: System Memory Read Command line. Indicates a memory read in the lower 1 MB area. This System Memory Read is an active-low signal which instructs memory devices to drive data onto the data bus SD0-SD15. This signal is active only when the memory address is within the lowest 1MB of memory address space.
• SMEMW: System Memory Write Commmand line. Indicates a memory write in the lower 1 MB area. The System Memory Write is an active-low signal which instructs memory devices to store data preset on the data bus SD0-SD15. This signal is active only when the memory address is within the lowest 1MB of memory address space.
• T/C: Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete. Terminal Count provides a pulse when the terminal count for any DMA channel is reached.

References

• IBM Personal Computer AT Technical Reference (5170) — Internet Archive
• EISA Bus Specification (BCPR Services) — Internet Archive
• MARK SOKOS (sokos@desupernet.net - http://users.desupernet.net/sokos)
• ISA bus information
• ISA bus pinout
• ISA BUS pinout
• ISA bus technical information

Category:Buses Connectors