Compact PCI

CompactPCI (PICMG 2.0) is an adaptation of the Peripheral Component Interconnect bus to the Eurocard mechanical form factor, designed for industrial, telecommunications, and embedded computing applications. It was ratified by the PCI Industrial Computer Manufacturers Group as PICMG 2.0 R3.0 (October 1999) and uses the IEC-1076 international standard 2 mm Hard Metric connector with 47 rows of 5 pins per row (220 pins total, with 15 lost to keying). A 3U board carries one or two connector segments (J1 for mandatory 32-bit PCI signals, J2 for optional 64-bit PCI or rear I/O), while a 6U board adds J3/J4/J5 for telephony, Ethernet, or user-defined I/O; up to eight slots may be populated on a single backplane, and 32-bit and 64-bit boards can be freely intermixed. The connector presented here is the full 7-column × 47-row (329-position) backplane connector, where columns Z and F carry ground, and columns A–E carry the PCI and CompactPCI-specific signals.

7×47 PIN (IEC917 and IEC1076-4-101) CONNECTOR at the backplane.

7×47 PIN (IEC917 and IEC1076-4-101) CONNECTOR at the device (card).

Overview:

A CompactPCI system is composed of up to eight CompactPCI card locations:

• One System Slot
• Up to seven Peripheral Slots

The connector has 7 columns with 47 rows. They are divided into groups:

• Row 1-25: 32-bit PCI
• Row 26-47: Additional pins for 64-bit PCI (System Slot boards must use it).
• Row 26-28 and 40-42: Primarily implemented on System Slot boards.

The following signals must be terminated:

• AD0-31
• C/BE0#-C/BE3#
• PAR
• FRAME#
• IRDY#
• TRDY#
• STOP#
• LOCK#
• IDSEL
• DEVSEL#
• PERR#
• SERR#
• RST#

The following signals must be terminated if used:

• INTA#
• INTB#
• INTC#
• INTD#
• SB0#
• SDOBE
• AD32-AD63
• C/BE4#-C/BE7#
• REQ64#
• ACK64#
• PAR64#

The following signals do no require a stub termination:

• CLK
• REQ#
• GNT#
• TDI#
• TDO
• TCK
• TMS
• TRST#

The System Slot board must pullup the following signals (even if not used):

• REQ64#
• ACK64#

Connector:

Notes

Rows 1–25 carry the mandatory 32-bit PCI signals; rows 26–47 carry optional 64-bit PCI extensions and CompactPCI-specific management signals. Rows 26–28 and 40–42 are primarily implemented on System Slot boards. The keying area (rows 12–14) prevents incorrect card insertion. V(I/O) pins supply either +3.3 V or +5 V depending on the signalling environment supported by the backplane; boards that support only one voltage must not violate the keying rules inherited from the PCI Local Bus Specification. Clock signals CLK1–CLK4 are distributed point-to-point by the System Slot board to each peripheral slot; the per-slot frequency is the same bus clock (33 MHz standard, optionally 66 MHz per PCI Rev 2.1 onward). REQ#/GNT# pairs are also point-to-point from the arbiter on the System Slot board to each peripheral slot. Signal termination requirements: all mandatory 32-bit PCI signals must be terminated; 64-bit extension signals (AD32–AD63, C/BE4#–C/BE7#, REQ64#, ACK64#, PAR64) must be terminated only if used; CLK, REQ#, GNT#, and JTAG signals (TDI, TDO, TCK, TMS, TRST#) do not require stub termination. The System Slot board must pull up REQ64# and ACK64# even when 64-bit mode is not used.

Signals

• AD(0)–AD(31) — Multiplexed 32-bit Address/Data bus; address is driven during the address phase and data during subsequent data phases.
• AD(32)–AD(63) — Optional 64-bit extension of the Address/Data bus; present in rows 26–39.
• C/BE(0)#–C/BE(3)# — Command/Byte Enable lines for 32-bit transfers; encode the bus command during the address phase and byte enables during data phases.
• C/BE(4)#–C/BE(7)# — Byte Enable lines for 64-bit data extension.
• PAR — Even parity over AD(0)–AD(31) and C/BE(0)#–C/BE(3)# for the preceding cycle.
• PAR64 — Even parity over AD(32)–AD(63) and C/BE(4)#–C/BE(7)# for the 64-bit extension.
• FRAME# — Cycle Frame; asserted by the current bus master to indicate that a bus transaction is in progress.
• IRDY# — Initiator Ready; asserted by the bus master to indicate it is ready to complete a data phase.
• TRDY# — Target Ready; asserted by the target device to indicate it is ready to complete a data phase.
• DEVSEL# — Device Select; asserted by the target that has decoded its address as the current transaction target.
• STOP# — Stop; asserted by the target to request the master halt the current transaction.
• LOCK# — Lock; asserted by the master to perform an indivisible (locked) transaction sequence.
• PERR# — Parity Error; asserted by any agent that detects a data parity error during a transaction.
• SERR# — System Error; asserted by any agent to report an address parity error or other serious condition.
• IDSEL — Initialisation Device Select; used during configuration read/write transactions to select individual devices.
• REQ# — Bus Request; point-to-point signal from a peripheral slot to the arbiter requesting bus ownership.
• GNT# — Bus Grant; point-to-point signal from the arbiter to a peripheral slot granting bus ownership.
• REQ1#–REQ6# — Additional per-slot bus request lines routed to the System Slot arbiter.
• GNT1#–GNT6# — Additional per-slot bus grant lines driven by the System Slot arbiter.
• REQ64# — 64-bit Transfer Request; asserted by the bus master to request a 64-bit data transfer; must be pulled up by the System Slot board.
• ACK64# — 64-bit Transfer Acknowledge; asserted by the target to confirm it can complete a 64-bit transfer; must be pulled up by the System Slot board.
• INTA#, INTB#, INTC#, INTD# — PCI interrupt request lines, active-low, open-drain; routed via the backplane to the System Slot interrupt controller.
• INTS — CompactPCI-specific interrupt signal (System Slot–only; exact routing is implementation-defined).
• INTP — CompactPCI-specific interrupt signal (System Slot–only; exact routing is implementation-defined).
• CLK — Primary PCI bus clock; 33 MHz standard, 66 MHz optional (per PCI Local Bus Specification Rev 2.1+).
• CLK1–CLK4 — Point-to-point PCI clock signals distributed by the System Slot board to individual peripheral slots.
• RST — PCI Reset; assertion resets all PCI devices on the bus.
• M66EN — 66 MHz Enable; sampled at reset to determine whether the bus is operating at 33 MHz or 66 MHz.
• SDONE — Snoop Done; asserted by the cache controller to indicate that snooping of the current transaction is complete.
• SBO# — Snoop Backoff; asserted by the cache controller to indicate a cache-line hit that requires intervention.
• TCK — JTAG Test Clock.
• TMS — JTAG Test Mode Select.
• TDI — JTAG Test Data Input (serial data shifted into the device under test).
• TDO — JTAG Test Data Output (serial data shifted out from the device under test).
• TRST# — JTAG Test Logic Reset; asynchronously resets the JTAG TAP controller.
• SYSEN# — System Slot Enable; driven low by the backplane to identify the System Slot board; peripheral slot boards see this signal unasserted.
• FAL# — Power Supply Status Fail; CompactPCI-specific open-drain signal asserted by the power supply to indicate impending failure.
• DEG# — Power Supply Status Degrade; CompactPCI-specific open-drain signal asserted by the power supply to indicate degraded operation.
• PRST# — Push Button Reset; CompactPCI-specific signal connected to the front-panel reset button on the System Slot; asserts RST# to the bus.
• BRSV — Bused Reserved; pins reserved by the PICMG 2.0 specification and must not be used.
• USR — User Defined; available for proprietary backplane-specific signalling not defined by PICMG 2.0.
• V(I/O) — I/O signalling voltage supply; either +3.3 V or +5 V depending on the backplane’s signalling environment.

For more information see PCI Notes

References

• CompactPCI Technical Summary — PICMG 2.0 connector architecture (CADX Services)
• PCI Local Bus Specification, Revision 2.2 (December 1998) — PCI-SIG via Bitsavers/Internet Archive
• MARK SOKOS (sokos@desupernet.net )

Category:Buses Connectors