PCI Power Macintosh 7200, 7500, 8500, 9500

The Power Macintosh 7200, 7500, 8500, and 9500 series were Apple’s first PCI-based desktop computers, introduced from mid-1995 onwards. They implement the standard 32-bit, 33 MHz PCI Local Bus as defined by PCI Local Bus Specification Revision 2.1 (June 1995), using a 124-pin card-edge connector (62 contacts per side). The 7200, 7500, and 8500 each provide three PCI expansion slots, while the 9500 provides six. No Apple-proprietary deviation from the PCI-SIG specification applies to these slots; standard PCI add-in cards designed for 5 V or universal signalling are compatible.

Notes

• These slots implement the PCI Local Bus Specification Revision 2.1 (June 1995) — the revision current when the Power Macintosh 9500 (May 1995), 7500, 7200, and 8500 shipped.
• The connector is a standard 32-bit PCI card-edge type: 62 contacts per side (124 total), with the 5 V keying notch at positions 12–13 and the 3.3 V keying notch at positions 50–51. These slots are 5 V environments; the keying notch at pins 50–51 (Connector Key rows) prevents insertion of 3.3 V-only cards.
• Bus clock is 33 MHz synchronous. The optional 66 MHz mode introduced in Rev 2.1 is not used on these models.
• The 7200, 7500, and 8500 provide three PCI slots; the 9500 provides six PCI slots.
• REQ64# and ACK64# at pins 60–61 are present on the connector but the bus operates in 32-bit mode on these machines; 64-bit cards will negotiate down to 32-bit operation.
• Add-in cards must comply with Apple’s interrupt routing, DMA, and Open Firmware ROM requirements as documented in the Apple PCI developer guide.

Signals

• AD[31:0] — Multiplexed 32-bit address/data bus; address is driven during the address phase, data during data phases.
• C/BE[3:0]# — Combined command/byte-enable lines; carry bus command during address phase and byte-enable signals during data phase.
• FRAME# — Cycle frame; driven by the current bus master to indicate the start and duration of an access.
• IRDY# — Initiator ready; asserted by the bus master when it is ready to complete the current data phase.
• TRDY# — Target ready; asserted by the target when it is ready to complete the current data phase.
• DEVSEL# — Device select; driven by the target to indicate it has decoded its address.
• STOP# — Stop; driven by the target to request the master to halt the current transaction.
• LOCK# — Lock; used to ensure exclusive access to a target across multiple transactions.
• IDSEL — Initialisation device select; used as a chip-select during configuration read/write transactions.
• PAR — Parity; even parity across AD[31:0] and C/BE[3:0]# for data integrity.
• PERR# — Parity error; reported by the target or master for data-phase parity errors.
• SERR# — System error; used to report address-phase parity errors and other critical errors.
• REQ# — Bus request; asserted by an agent to request use of the bus from the arbiter.
• GNT# — Bus grant; driven by the arbiter to indicate a requesting agent may use the bus.
• CLK — Bus clock; 33 MHz synchronous clock distributed to all agents.
• RST# — Reset; drives all PCI agents into a defined initial state.
• INTA#, INTB#, INTC#, INTD# — Interrupt request lines; open-drain, level-sensitive, active-low.
• PRSNT1#, PRSNT2# — Presence-detect pins; driven low by add-in cards to indicate their presence and power requirements to the system.
• SDONE — Snoop done; indicates the completion of a snoop cycle by a cache controller.
• SBO# — Snoop backoff; asserted to indicate a snoop hit on a modified cache line.
• TCK, TMS, TDI, TDO, TRST# — IEEE 1149.1 (JTAG) boundary-scan signals for board-level testing.
• REQ64# — 64-bit transfer request; used to initiate an optional 64-bit bus transaction (not active in 32-bit mode).
• ACK64# — 64-bit transfer acknowledgement; driven by the target to accept a 64-bit transaction (not active in 32-bit mode).
• +12V / -12V — Legacy ±12 V supply rails, retained from earlier ISA/AT bus conventions for analogue circuitry.
• +5V — Primary 5 V supply rail for PCI logic in 5 V signalling environments.
• +3.3V — 3.3 V supply rail; present on the connector but the 5 V signalling environment is primary on these models.
• +5V (I/O) — 5 V supply designated for I/O buffer power.
• Connector Key — Physical keying gap at positions 50–51 corresponding to the 3.3 V notch; prevents insertion of 3.3 V-only cards into these 5 V slots.

References

• Designing PCI Cards and Drivers for Power Macintosh Computers (Apple Developer Library)
• PCI Local Bus Specification, Revision 2.1 (June 1995) — PCI-SIG, archived by Bitsavers / Internet Archive
• PCI Local Bus Specification, Revision 2.2 (December 1998) — PCI-SIG, archived by Bitsavers / Internet Archive

Category:Buses Connectors