The Amiga 1200 CPU port — commonly called the trapdoor slot — is a 150-pin card edge connector (male) located on the underside of the PCB, accessible via a removable bottom panel. Specified in the Commodore-Amiga A1200/A1200HD System Functional Specification (Revision 1.6, October 1992), it exposes the full 32-bit data bus and 24-bit address bus of the Motorola 68EC020 processor running at 14 MHz. The connector is intended for processor accelerator cards, fast RAM expansion, and DMA SCSI controllers, and its fine 50 mil (0.050 inch) pin pitch distinguishes it from the coarser Zorro II/III bus connectors used in desktop Amiga models.
| Pin | Name | Description |
|---|---|---|
| 1 | n/c | Reserved |
| 2 | n/c | Reserved |
| 3 | n/c | Reserved |
| 4 | n/c | Reserved |
| 5 | n/c | Reserved |
| 6 | n/c | Reserved |
| 7 | n/c | Reserved |
| 8 | n/c | Reserved |
| 9 | GND | Ground |
| 10 | +5V | +5 Volts DC |
| 11 | A23 | Address 23 |
| 12 | A22 | Address 22 |
| 13 | A21 | Address 21 |
| 14 | A20 | Address 20 |
| 15 | A19 | Address 19 |
| 16 | A18 | Address 18 |
| 17 | A17 | Address 17 |
| 18 | A16 | Address 16 |
| 19 | GND | Ground |
| 20 | +5V | +5 Volts DC |
| 21 | A15 | Address 15 |
| 22 | A14 | Address 14 |
| 23 | A13 | Address 13 |
| 24 | A12 | Address 12 |
| 25 | A11 | Address 11 |
| 26 | A10 | Address 10 |
| 27 | A9 | Address 9 |
| 28 | A8 | Address 8 |
| 29 | GND | Ground |
| 30 | +5V | +5 Volts DC |
| 31 | A7 | Address 7 |
| 32 | A6 | Address 6 |
| 33 | A5 | Address 5 |
| 34 | A4 | Address 4 |
| 35 | A3 | Address 3 |
| 36 | A2 | Address 2 |
| 37 | A1 | Address 1 |
| 38 | A0 | Address 0 |
| 39 | GND | Ground |
| 40 | +5V | +5 Volts DC |
| 41 | D31 | Data 31 |
| 42 | D30 | Data 30 |
| 43 | D29 | Data 29 |
| 44 | D28 | Data 28 |
| 45 | D27 | Data 27 |
| 46 | D26 | Data 26 |
| 47 | D25 | Data 25 |
| 48 | D24 | Data 24 |
| 49 | GND | Ground |
| 50 | +5V | +5 Volts DC |
| 51 | D23 | Data 23 |
| 52 | D22 | Data 22 |
| 53 | D21 | Data 21 |
| 54 | D20 | Data 20 |
| 55 | D19 | Data 19 |
| 56 | D18 | Data 18 |
| 57 | D17 | Data 17 |
| 58 | D16 | Data 16 |
| 59 | GND | Ground |
| 60 | +5V | +5 Volts DC |
| 61 | D15 | Data 15 |
| 62 | D14 | Data 14 |
| 63 | D13 | Data 13 |
| 64 | D12 | Data 12 |
| 65 | D11 | Data 11 |
| 66 | D10 | Data 10 |
| 67 | D9 | Data 9 |
| 68 | D8 | Data 8 |
| 69 | GND | Ground |
| 70 | +5V | +5 Volts DC |
| 71 | D7 | Data 7 |
| 72 | D6 | Data 6 |
| 73 | D5 | Data 5 |
| 74 | D4 | Data 4 |
| 75 | D3 | Data 3 |
| 76 | D2 | Data 2 |
| 77 | D1 | Data 1 |
| 78 | D0 | Data 0 |
| 79 | GND | Ground |
| 80 | +5V | +5 Volts DC |
| 81 | /IPL2 | |
| 82 | /IPL1 | |
| 83 | /IPL0 | |
| 84 | n/c | Reserved |
| 85 | /RST | Reset |
| 86 | /HLT | Halt |
| 87 | n/c | Reserved |
| 88 | n/c | Reserved |
| 89 | SIZE1 | |
| 90 | SIZE0 | |
| 91 | /AS | Address Strobe |
| 92 | /DS | Data Strobe |
| 93 | R/W | Read/Write |
| 94 | /BERR | Bus Error |
| 95 | n/c | Reserved |
| 96 | /AVEC | |
| 97 | /DSACK1 | |
| 98 | /DSACK2 | |
| 99 | CPUCKLA | |
| 100 | ECLOCK | EClock pulse |
| 101 | GND | Ground |
| 102 | +5V | +5 Volts DC |
| 103 | FC2 | Processor Status 2 |
| 104 | FC1 | Processor Status 1 |
| 105 | FC0 | Processor Status 0 |
| 106 | /RMC | |
| 107 | n/c | Reserved |
| 108 | n/c | Reserved |
| 109 | n/c | Reserved |
| 110 | n/c | Reserved |
| 111 | /BR | Slot specific Bus Arbitration |
| 112 | /BG | Slot specific Bus Arbitration |
| 113 | n/c | Reserved |
| 114 | /BOSS | |
| 115 | /FPUCS | FPU Chip select |
| 116 | /FPUSENSE | FPU Sense |
| 117 | CCKA | |
| 118 | /RESET | Reset |
| 119 | GND | Ground |
| 120 | +5V | +5 Volts DC |
| 121 | /NETCS | |
| 122 | /SPARECS | |
| 123 | /RTCCS | Realtime Clock Chip select |
| 124 | /FLASH | |
| 125 | /REG | |
| 126 | /CCENA | |
| 127 | /WAIT | |
| 128 | /KBRESET | Keyboard reset |
| 129 | /IORD | IO Read |
| 130 | /IOWR | IO Write |
| 131 | /OE | Output enable |
| 132 | /WE | |
| 133 | /OVR | /DTACK Override |
| 134 | XRDY | External Ready |
| 135 | /ZORRO | |
| 136 | /WIDE | |
| 137 | /INT2 | Interrupt level 2 |
| 138 | /INT6 | Interrupt level 6 |
| 139 | GND | Ground |
| 140 | +5V | +5 Volts DC |
| 141 | SYSTEM1 | System1 Ground |
| 142 | SYSTEM0 | System0 Ground |
| 143 | /xRxD | |
| 144 | /xTxD | |
| 145 | /CONFIG OUT | |
| 146 | AGND | Audio Ground |
| 147 | ALEFT | Audio Left |
| 148 | ARIGHT | Audio Right |
| 149 | +12V | +12 Volts DC |
| 150 | -12V | -12 Volts DC |
Notes
- The connector is a card edge type (male) with 50 mil (0.050 inch) pin spacing — significantly finer than the 100 mil pitch used on the Zorro II/III bus connectors in the A2000/A3000/A4000.
- Expansion cards mount upside-down in the L-shaped internal space beneath the A1200 motherboard, in a manner similar to the earlier A601 memory expansion for the A600.
- Power available to expansion cards is limited: +5 V at up to 250 mA across 11 pins, +12 V at 25 mA on one pin, and −12 V at 25 mA on one pin, with 11 GND pins.
- The CPU fitted in the A1200 is the 68EC020, a cost-reduced variant of the 68020 that omits the external cache control signals and restricts the address bus to 24 bits (A23–A0) despite the processor’s internal 32-bit address capability.
- System clock (_CPUCLK_A) runs at 14 MHz; the colour clock (CCK_A) runs at approximately 3.58 MHz.
- Pin 99 (CPUCKLA) and pin 117 (CCKA) carry the CPU clock and colour clock signals respectively to the expansion card.
- The /CONFIG OUT signal on pin 145 is part of the AutoConfig daisy-chain used by Zorro-style self-configuring cards.
- Signals marked n/c (pins 1–8, 84, 87, 88, 95, 107–110, 113) are reserved and should not be driven.
Signals
- A23–A0 — 24-bit address bus from the 68EC020 processor
- D31–D0 — 32-bit data bus; full longword width exposed to expansion cards
- FC2–FC0 — Processor function code lines indicating the type of bus cycle (supervisor/user, data/program/CPU space)
- _AS — Address Strobe: asserted by the CPU when a valid address is present on the bus
- _DS — Data Strobe: asserted to indicate valid data on a write or to request data on a read
- R/_W — Read/Write direction line; high = read, low = write
- _DSACK0, _DSACK1 — Data and Size Acknowledge inputs to the CPU; used by peripherals to signal transfer completion and port width (pins 97 and 98, labelled /DSACK1 and /DSACK2 in the original table)
- _IPL2–_IPL0 — Interrupt Priority Level inputs to the CPU (pins 81–83)
- _INT2, _INT6 — Amiga bus interrupt request lines at levels 2 and 6
- _RST — Reset signal; can be driven by the expansion card to initiate a system reset
- _HLT — Halt signal; asserted to suspend CPU bus activity
- _BERR — Bus Error: informs the CPU that the current bus cycle has failed
- _AVEC — Autovector input; causes the CPU to generate an internal interrupt vector rather than fetching one from the bus
- SIZE1, SIZE0 — Transfer size outputs from the CPU indicating byte, word, or longword transfer (pins 89–90)
- _RMC — Read–Modify–Write Cycle indicator (pin 106); used by the CPU during atomic operations
- _BR, _BG — Bus Request and Bus Grant for slot-specific bus arbitration (pins 111–112)
- _BOSS — Indicates that an accelerator card has taken over as the system’s active processor (pin 114)
- _FPUCS — Chip select for an optional floating-point unit on the expansion card (pin 115)
- _FPUSENSE — Sense line used to detect whether an FPU is fitted (pin 116)
- CPUCKLA — 14 MHz CPU clock output from the motherboard to the expansion card (pin 99)
- CCKA — Colour clock signal at approximately 3.58 MHz (pin 117)
- ECLOCK — E-clock pulse compatible with 6800-family peripheral timing (pin 100)
- _RESET — Motherboard reset line (pin 118); distinct from _RST
- _NETCS — Chip select for on-board network/ethernet circuitry (pin 121)
- _SPARECS — Spare chip select available for expansion use (pin 122)
- _RTCCS — Chip select for the real-time clock (pin 123)
- _FLASH — Chip select for flash ROM (pin 124)
- _REG — Register select signal (pin 125)
- _CCENA — Colour clock enable (pin 126)
- _WAIT — Wait state request input (pin 127)
- _KBRESET — Keyboard reset signal (pin 128)
- _IORD, _IOWR — I/O read and write strobes (pins 129–130)
- _OE — Output enable for memory or bus buffers (pin 131)
- _WE — Write enable for memory (pin 132)
- _OVR — DTACK Override; allows an expansion card to suppress the default bus termination (pin 133)
- XRDY — External Ready; asserts readiness to the CPU (pin 134)
- _ZORRO — Indicates a Zorro-compatible expansion card is present (pin 135)
- _WIDE — Signals that the expansion card uses a wide (32-bit) data bus (pin 136)
- SYSTEM1, SYSTEM0 — System ground reference signals (pins 141–142)
- _xRxD, _xTxD — Auxiliary serial receive and transmit lines (pins 143–144)
- _CONFIG OUT — AutoConfig daisy-chain output; passed to the next expansion device in the chain (pin 145)
- AGND — Analogue ground reference for audio circuitry (pin 146)
- ALEFT, ARIGHT — Left and right analogue audio signals (pins 147–148)
- +5V — 5 V DC supply (11 pins, up to 250 mA total to expansion card)
- +12V — +12 V DC supply (1 pin, up to 25 mA)
- −12V — −12 V DC supply (1 pin, up to 25 mA)
- GND — Digital ground (11 pins)
References
- A1200/A1200HD Advanced Amiga 1200 System Functional Specification, Revision 1.6 — Commodore-Amiga, Inc., October 1992
- Amiga Hardware Reference Manual, 3rd Edition — Commodore-Amiga Inc., 1991