Unibus

UNIBUS is Digital Equipment Corporation’s proprietary asynchronous backplane bus, introduced in 1970 with the PDP-11/20 minicomputer and specified in DEC’s 1979 UNIBUS Specification. It carries 16 data lines (D00–D15) and 18 address lines (A00–A17), giving a 256 KB physical address space of which the top 8 KB (addresses 760000–777777 octal) is permanently reserved for device registers. The bus is fully asynchronous, using MSYN (Master Sync) and SSYN (Slave Sync) handshake signals rather than a fixed clock, and supports five interrupt priority levels (NPR, BR7–BR4) for up to 20 devices per segment over a maximum cable run of 15.24 m (50 ft). All signals are active-low, pulled to +5 V by terminators at each end of the bus.

The A and B connectors described below are used only for “Modified Unibus Devices” such as bus extenders, terminators, and repeaters. Notably the type “2” signals only appear on one pin each. This is acceptable on the A and B connectors because each bus segment has a bus-in connector at one end and a bus-out at the other, and the type “2” signals are broken when they run through the C, D, E, and F connectors. Unibus boards that use the C, D, E, and F connectors are called “Small Peripheral Controllers”. Hex boards plug into the A and B connectors as well but do not pick up any signals from them (including power or ground).

A, B connectors pinouts

2 x 36 EDGE FEMALE at the backplane

2 x 36 EDGE MALE at the cards/modules

C, D, E and F connectors pinouts

Unknow connector

Notes

• The original UNIBUS cable (BC11A) uses two 36-conductor Flexprint ribbon cables (120 conductors total; every alternate trace grounded for crosstalk suppression). Later installations used three 2×20 Berg flat-cable headers (H854 variant) via M9014/M9042 transition cards.
• All UNIBUS signals are active-low (asserted to ground); bus terminators at both ends of the daisy-chain hold lines high (+5 V) when idle.
• Each bus segment requires a terminator at both the “bus in” and “bus out” ends. The maximum segment length is 15.24 m (50 ft); a repeater extends the bus by a further 50 ft.
• The A and B connectors expose a 2×36 edge connector at the backplane (female) and on cards/modules (male). The C, D, E, and F connectors serve Small Peripheral Controllers and carry all 56 UNIBUS signal lines across multiple Berg headers.
• Power is +5 V only; UNIBUS does not supply ±12 V or −5 V rails.
• Four transfer cycle types are defined: DATI (read word or byte), DATIP (read-modify-write start), DATO (write word), and DATOB (write byte).
• Bus grant lines (NPG, BG7–BG4) are daisy-chained through each device in physical slot order; a device without a board present must bridge the grant line through to the next slot.
• UNIBUS should not be confused with the Q-Bus, which is a narrower 56-signal bus used in later PDP-11 and VAXstation models.

Signals

A and B connector signals

• /INIT — Bus initialisation; asserted by the processor to reset all devices.
• /ACLO — AC power low; warns devices of impending power loss.
• /DCLO — DC power low; indicates DC supplies have fallen out of tolerance.
• /INTR — Interrupt request; asserted by a device to request a processor interrupt.
• /BR7–/BR4 — Bus request lines at priority levels 7 through 4; devices assert to request the bus for interrupt service.
• BG7–BG4 — Bus grant lines for BR7–BR4; processor asserts to grant the bus; daisy-chained through device slots.
• /NPR — Non-Processor Request; highest-priority DMA request line used by direct-memory-access devices.
• NPG — Non-Processor Grant; asserted by processor to grant DMA access; daisy-chained.
• /BBSY — Bus Busy; asserted by the current bus master to indicate the bus is in use.
• /SACK — Selection Acknowledge; asserted by a device that has accepted a bus grant before taking control.
• /MSYN — Master Sync; asserted by the bus master to indicate a valid address/data phase has begun.
• /SSYN — Slave Sync; asserted by the addressed slave to acknowledge the MSYN phase.
• /C0, /C1 — Cycle-type control lines; together encode the four UNIBUS transfer types (DATI, DATIP, DATO, DATOB).
• /PA, /PB — Parity lines A and B; used for optional bus parity checking.
• /D00–/D15 — 16 bidirectional data lines; carry the 16-bit data word.
• /A00–/A17 — 18 address lines; define the 256 KB physical address space (top 8 KB reserved for device registers).
• POWER (+5V) — +5 V supply provided to devices via the backplane.
• GROUND — Signal and power return.

References

• DEC UNIBUS Specification 1979 (archived by Bitsavers / Internet Archive)

Category:Buses Connectors