VME (VERSAmodule Eurocard) P1

VME P1 Connector - 96 pin DIN (41612, Type C) 3 rows x 32 pins [Pitch 2.54mm (.100")] @ IEEE 1014-1987

VMEbus (VERSAmodule Eurocard bus) is a parallel computer backplane bus architecture developed in 1980–1981 by Motorola, Mostek, and Signetics, combining the VERSAbus electrical standard with the Eurocard mechanical form factor; VERSAbus itself had been defined by Motorola in 1979 for its 68000 microprocessor. The P1/J1 connector uses a 96-pin DIN 41612 Type C (IEC 60603-2) body — three rows (A, B, C) of 32 positions at 2.54 mm pitch — and carries all bus arbitration, control, interrupt, address (A01–A23), and data (D00–D15) signals required by the original IEEE 1014-1987 specification. The bus is asynchronous, relying on handshake signals rather than a central clock; the 16 MHz SYSCLK pin is a utility clock only, not a bus timing reference. Note that pins B21 (SERCLK) and B22 (SERDAT*) were renamed SERA and SERB in the later ANSI/VITA 1-1994 (VME64) revision for generic serial bus use; this page documents the original IEEE 1014-1987 signal names.

Notes

• (*) Active Low.
• The P1/J1 connector is a standard 96-pin DIN 41612 Type C body (IEC 60603-2), rated at 2 A per contact, with 2.54 mm pitch. It mates with the corresponding J1 backplane receptacle.
• 3U single-height Eurocards (160 × 100 mm) use P1 only; 6U double-height boards (160 × 233 mm) use both P1 and P2/J2 for full 32-bit addressing and data.
• VME64x boards add two further rows (z and d) around the outside of the DIN 41612 body to create a 160-pin connector; 96-pin P1 boards remain backward-compatible with 160-pin VME64x backplane sockets.
• Backplanes support a maximum of 21 slots at 0.8 inch (20.32 mm) pitch.
• The VMEbus signal drive types are:
  • Open collector — ACFAIL*, BBSY*, BERR*, DTACK*, IACK*, SERDAT*, SYSFAIL*, SYSRESET*, IRQ1*–IRQ7*, BR0*–BR3*.
  • Three-state — AS*, DS0*, DS1*, IACK*, LWORD*, WRITE*, AM0–AM5, A01–A31, D00–D31.
  • Totem-pole — BCLR*, SYSCLK, SERCLK, IACKIN*, IACKOUT*, BG0IN*–BG3IN*, BG0OUT*–BG3OUT*.

Signals

• D00–D15 — Data bus lines (bits 0–15); driven three-state.
• D08–D15 (Row C, pins 1–8) — Upper byte of the 16-bit data bus on P1.
• A01–A23 — Address bus lines; provide up to 16 MB (A24) addressing on P1 alone. A01 is the least-significant address bit.
• AM0–AM5 — Address Modifier lines; encode the address space and transfer type for each bus cycle.
• BBSY* — Bus Busy; open-collector line asserted by the current bus master to indicate ownership of the bus.
• BCLR* — Bus Clear; totem-pole output from the arbiter requesting the current master to release the bus.
• ACFAIL* — AC Fail; open-collector warning that the AC power supply is failing, giving boards time to perform an orderly shutdown before power is lost.
• BG0IN*–BG3IN* — Bus Grant In for priority levels 0–3; daisy-chained token passed from the arbiter slot-by-slot down the backplane.
• BG0OUT*–BG3OUT* — Bus Grant Out for priority levels 0–3; passed to the next slot in the daisy chain.
• BR0*–BR3* — Bus Request lines for priority levels 0–3; open-collector signals from potential masters to the arbiter.
• DS0*, DS1* — Data Strobe lines; indicate the validity of data on the bus and define the byte lane(s) being accessed.
• AS* — Address Strobe; indicates that a valid address and address modifier are present on the bus.
• WRITE* — Indicates transfer direction: asserted (low) for a write cycle, negated (high) for a read cycle.
• DTACK* — Data Transfer Acknowledge; open-collector response from the addressed slave confirming data transfer completion.
• LWORD* — Long Word; asserted during 32-bit data transfers to indicate all four byte lanes are active.
• IACK* — Interrupt Acknowledge; open-collector signal indicating an IACK cycle is in progress.
• IACKIN*, IACKOUT* — Interrupt Acknowledge daisy-chain In/Out; totem-pole signals passed slot-to-slot to locate the interrupting device.
• IRQ1*–IRQ7* — Interrupt Request lines (priority 1–7, level 7 highest); open-collector, wired-OR across all slots.
• SYSCLK — 16 MHz utility clock provided by the System Controller slot; used for timing reference by boards that require it but is not a VMEbus transfer clock.
• SYSFAIL* — System Fail; open-collector line asserted by any board detecting a serious fault.
• BERR* — Bus Error; open-collector signal from a slave or the System Controller indicating an abnormal bus condition.
• SYSRESET* — System Reset; open-collector line that resets all boards on the backplane.
• SERCLK — Serial Clock for the VMEbus serial sub-bus (IEEE 1014-1987 name; renamed SERA in ANSI/VITA 1-1994).
• SERDAT* — Serial Data for the VMEbus serial sub-bus (IEEE 1014-1987 name; renamed SERB in ANSI/VITA 1-1994).
• +5 V — Primary logic supply.
• +12 V, -12 V — Auxiliary analogue supplies.
• +5 V Standby — Standby supply maintained when the main +5 V rail is off; used for memory backup and wake-on-event logic.
• GND — Signal/power ground.

References

• VMEbus Frequently Asked Questions (FAQ) — VITA (VMEbus International Trade Association)
• VITA Standards Access — VITA; index of governing standards including IEEE 1014-1987, ANSI/VITA 1-1994, and ANSI/VITA 1.1-1997
• Motorola / Micrology VMEbus Specification Manual, Rev C.1, October 1985 — archived pre-IEEE primary source via Internet Archive / bitsavers.org
• DIN 41612 Connectors — Product Overview — HARTING Technology Group; mechanical specification for the DIN 41612 Type C and 160-pin VME64x connectors

Category:Buses Connectors