TI-99/4A Card Slot (Inside PE Box)

60-pin card-edge connector for the TI-99/4A Peripheral Expansion Box, carrying an 8-bit data bus, 16-bit address bus, CRU serial I/O, and unregulated power rails.

TI-99/4A PE-box card slot, 60-pin edge

60-pin card-edge connector.

The TI-99/4A Peripheral Expansion Box (PE Box), introduced alongside the TI-99/4A home computer in the early 1980s, uses a 60-pin card-edge bus to connect expansion cards. The connector carries an 8-bit data bus (D0–D7), a 16-bit address bus (A0–A15), and the TI-99/4A’s unique Communications Register Unit (CRU) serial I/O lines. Power is supplied as unregulated voltages — approximately +8 V, −16 V, and +16 V — that each expansion card must regulate locally to ±5 V or ±12 V as required. The bus is defined in Texas Instruments’ 1983 document Console And Peripheral Expansion System Technical Data, which remains the primary hardware reference for card developers.

PinNameDirDescription
1+5V 3-T regulator voltage supply (about +8V)
2-Dito
3GND-Ground
4READYA-System ready (10K pull-up to +5V)
5GND-Ground
6RESET*OUTSystem reset (active low)
7GND-Ground
8SCLKncSystem clock (not connected)
9LCP*ncCPU indicator 1=TI99 0=2nd generation (not connected)
10AUDIOINInput audio (=AUDIOIN)
11RDBENA*INActive low: enable flex cable data bus drivers (1K pull-up)
12PCBENHPCB enable for burn-in (always High)
13HOLD*HActive low CPU hold request (always High)
14IAQHAncIAQ [or] HOLDA (logical or)
15SENILA*HInterrupt level A sense enable (always High)
16SENILB*HInterrupt level B sense enable (always High)
17INTA*INActive low interrupt level A (=EXTINT*)
18LOAD*ncUnmaskable interrupt (not connected)
19D7IN/OUTData bus, bit 7 (least significant)
20GND-Ground
21D5IN/OUT
22D6IN/OUT
23D3IN/OUT
24D4IN/OUT
25D1IN/OUT
26D2IN/OUT
27GND-Ground
28D0IN/OUTData bus, bit 0 (most significant)
29A14OUT
30A15OUTAddress bus, lsb. Also CRU output bit.
31A12OUT
32A13OUT
33A10OUT
34A11OUT
35A8OUT
36A9OUT
37A6OUT
38A7OUT
39A4OUT
40A5OUT
41A2OUT
42A3OUT
43A0OUTAddress bus, bit 0 (most significant)
44A1OUT
45AMBHExtra address bit. Always High.
46AMAHExtra address bit. Always High.
47GND-Ground
48AMCHExtra address bit. Always High.
49GND-Ground
50CLKOUT*OUTInversion of phase 3 clock (=PHI3*)
51CRUCLK*OUTInversion of TMS9900 CRUCLOCK pin
52DBINOUTActive high = read memory
53GND-Ground
54WE*OUTWrite Enable (derived from TMS9900 WE* pin)
55CRUININCRU input bit to TMS9900
56MEMEN*OUTMemory access enable (active low)
57-12 Volts 3-T regulator supply voltage (about -16V)
58Dito
59+12 Volts 3-T regulator supply voltage (about +16V)
60Dito

Signals

  • D0–D7 — 8-bit bidirectional data bus. Note that by TI convention D7 is the least significant bit and D0 is the most significant bit, the reverse of most other architectures.
  • A0–A15 — 16-bit address bus, output from the CPU. A0 is the most significant bit; A15 is the least significant and doubles as the CRU output bit for serial I/O addressing.
  • AMA, AMB, AMC — Extra address bits always driven High; used to extend the address space for future expansion.
  • DBIN — Data Bus IN; active high indicates a memory read cycle.
  • WE* — Write Enable; active low, derived from the TMS9900 WE* pin.
  • MEMEN* — Memory access enable; active low, qualifies address bus for memory (as opposed to CRU) cycles.
  • CRUCLK* — Inverted TMS9900 CRUCLOCK signal; clocks CRU serial output shifts.
  • CRUIN — CRU serial input bit returning data to the TMS9900.
  • READYA — System ready signal with 10 kΩ pull-up to +5 V; expansion cards may hold this low to insert wait states.
  • RESET* — Active-low system reset, output from the PE Box backplane.
  • RDBENA* — Active-low signal that enables the flex-cable data bus drivers (74LS245); 1 kΩ pull-up.
  • INTA* — Active-low interrupt level A, equivalent to EXTINT*.
  • SENILA*, SENILB* — Interrupt level sense enables; always driven High in the base system.
  • PCBEN — PCB burn-in enable; always High in normal operation.
  • HOLD* — Active-low CPU hold request; always High (not used).
  • IAQHA — Logical OR of IAQ (Instruction Acquisition) and HOLDA; not connected in the standard PE Box.
  • LOAD* — Unmaskable interrupt input; not connected in the standard PE Box.
  • SCLK — System clock; not connected in the standard PE Box.
  • LCP* — CPU indicator (1 = TI-99/4A, 0 = second-generation CPU); not connected in the standard PE Box.
  • CLKOUT* — Inverted phase-3 clock output (PHI3*).
  • AUDIO — Analogue audio input to the PE Box sound mixing circuit.
  • Pins 1–2 — Unregulated +8 V supply (nominal; for +5 V regulation on card).
  • Pins 57–58 — Unregulated −16 V supply (nominal; for −12 V regulation on card).
  • Pins 59–60 — Unregulated +16 V supply (nominal; for +12 V regulation on card).

Notes

  • The connector is a 60-pin card-edge type; pin numbering runs from rear (odd side, pins 1–59) to front (even side, pins 2–60) of the PE Box chassis.
  • Address and control signals are buffered by 74LS244 drivers in the flex-cable connection module: A0–A15, DBIN, MEMEN*, WE*, RESET*, CLKOUT*.
  • The data bus is buffered by two 74LS245 transceivers (one at each end of the flex cable), with 47 Ω series resistors; direction is controlled by DBIN, gated by RDBENA*.
  • Unbuffered signals passed directly: CRUIN, INTA*, AUDIO, READYA.
  • All signals must be re-buffered on each expansion card; the bus does not drive cards directly.
  • Always-High lines (AMA, AMB, AMC, SENILA*, SENILB*, PCBEN, HOLD*) are pulled up to +5 V via 47 Ω resistors on the backplane.
  • Power rails are unregulated; each card is responsible for on-board regulation to the required ±5 V or ±12 V levels.

References

Category:Buses Connectors