PC Card ATA

The PC Card ATA specification defines how ATA mass-storage devices — such as solid-state drives and hard discs — communicate over the standard 68-pin PC Card (PCMCIA) connector. Governed by the PCMCIA/JEIDA PC Card ATA Specification (Volume 8, Release 7.0, February 1999), it supplements both the ANSI ATA standard and the broader PC Card Standard without redefining the connector itself. The 68-pin card-edge socket carries two rows of 34 contacts at 1.27 mm (0.050 in) pitch, shared with 16-bit PCMCIA and CardBus cards. Two access modes are supported: I/O-mapped mode, using standard ATA register addresses (1F0–1F7h, 3F6–3F7h, or their secondary equivalents), and memory-mapped mode, placing the card into a 2 KB host memory window.

68 PIN MALE Connector at the controller

68 PIN FEMALE Connector at the peripherals

Notes

• x = Required.
• i = Ignored by host in ATA mode.
• o = Optional.
• nothing = Not connected.
• (1) Device shall support only one /CS1 signal pin.
• (2) Device shall support either M/S- or CSEL but not both.
• (3) Device shall hold this signal negated if it does not support this function.
• The 68-pin PC Card connector uses two rows of 34 contacts at 1.27 mm (0.050 in) pitch; all PC Card types (Type I 3.3 mm, Type II 5.0 mm, Type III 10.5 mm) share the same 68-pin socket and 85.6 mm × 54.0 mm card footprint.
• Two operating modes are defined: I/O-mapped mode maps ATA task-file registers to standard host I/O addresses (primary 1F0–1F7h / 3F6–3F7h, secondary 170–177h / 376–377h); memory-mapped mode places the card in a 2 KB host memory aperture.
• Vcc is supplied on pins 17 and 51; Vpp1/Vpp2 (pins 18 and 52) are recommended at +12 V if used, but may be left unconnected on devices that do not require a programming voltage.
• Both 8-bit and 16-bit data accesses are supported; the dual chip-enable signals /CS0 (CE1#) and /CS1 (CE2#) allow the host to select odd-address bytes on the 16-bit bus.

Signals

• DD0–DD15 — 16-bit bidirectional data bus (maps to PC Card D0–D15); DD8–DD15 carry the upper byte in 16-bit transfers.
• DA0–DA2 — Three-bit ATA task-file register address bus (maps to PC Card A0–A2); selects one of eight ATA registers within a chip-enable window.
• /CS0 — Active-low chip-select 0; selects the primary ATA task-file register block (maps to PC Card /CE1).
• /CS1 — Active-low chip-select 1; selects the alternate status / device control register (maps to PC Card /CE2 on pin 42, or A9 on pin 11 — device shall implement only one).
• /SELATA — Active-low signal asserted by the host to place the card in ATA mode; maps to PC Card /OE (output-enable).
• /DIOR — Active-low I/O read strobe issued by the host to read an ATA register (maps to PC Card /IORD).
• /DIOW — Active-low I/O write strobe issued by the host to write an ATA register (maps to PC Card /IOWR).
• INTRQ — Interrupt request asserted by the device to signal command completion or an error condition (maps to PC Card /READY:/IREQ).
• /IOCS16 — Active-low signal driven by the device to indicate that 16-bit I/O transfers are supported on the current cycle (maps to PC Card /WP:IOIS16).
• IORDY — I/O channel ready; device deasserts this signal to insert wait states when it cannot complete a transfer in the standard cycle time (maps to PC Card /WAIT); optional — device holds negated if not supported.
• DMARQ — DMA request asserted by the device when DMA data transfer is requested (maps to PC Card /INPACK); optional — device holds negated if not supported.
• /DMACK — Active-low DMA acknowledge driven by the host to initiate a DMA transfer cycle (maps to PC Card /REG); optional.
• /RESET — Active-low hardware reset driven by the host to initialise the device (maps to PC Card RESET).
• /DASP — Active-low signal used for device active / slave present detection during initialisation (maps to PC Card /BVD2:SPKR).
• /PDIAG — Active-low passed diagnostics signal exchanged between master and slave devices during the POST sequence (maps to PC Card /BVD1:STSCHG).
• M/S- — Master/slave configuration input; used to designate the device as master or slave when /CS1 is not available; device supports either M/S- or CSEL, not both.
• CSEL — Cable select input; determines master/slave role based on the physical position of the device on the interface cable; device supports either CSEL or M/S-, not both.
• /CD1, /CD2 — Active-low card detect signals driven by the socket; both must be asserted for the host to recognise a card as fully inserted (maps to PC Card /CD1 and /CD2).
• VCC — +3.3 V or +5 V power supply to the device (pins 17 and 51).
• Ground — Signal and power return (pins 1, 34, 35, 68).

References

• PC Card ATA Specification, Volume 8, Release 7.0 (February 1999) — PCMCIA/JEIDA
• PC Card Standard Release 8.0, Volume 2: Electrical Specification (April 2001) — PCMCIA/JEITA
• PC Card Standard Release 8.0, Volume 3: Physical Specification (April 2001) — PCMCIA/JEITA

Category:Buses Connectors