PCI Express 1x - 36 pin Female Connector
PCI Express (PCIe) is a high-speed serial expansion interface maintained by the PCI Special Interest Group (PCI-SIG); the base specification was published in 2002 and the bus reached mainstream PCs in 2003–2004. It replaces the shared parallel bus of conventional PCI with point-to-point serial links. A link is built from lanes, each lane being one differential pair per direction (dual-simplex); the x1 slot provides a single lane and is the smallest PCIe slot, used for lower-bandwidth expansion cards such as network, sound and capture cards. First-generation PCIe runs at 2.5 GT/s per lane per direction and the second generation at 5.0 GT/s, using 8b/10b encoding with an embedded clock. The x1 add-in card edge connector has 36 contacts, 18 on each side. The table below lists the Side B contacts.
| Pin | Name | Description |
|---|---|---|
| 1 | +12v | +12 volt power |
| 2 | +12v | +12 volt power |
| 3 | RSVD | Reserved |
| 4 | GND | Ground |
| 5 | SMCLK | SMBus clock |
| 6 | SMDAT | SMBus data |
| 7 | GND | Ground |
| 8 | +3.3v | +3.3 volt power |
| 9 | JTAG1 | +TRST# |
| 10 | 3.3Vaux | 3.3v volt power |
| 11 | WAKE# | Link Reactivation |
| 12 | RSVD | Reserved |
| 13 | GND | Ground |
| 14 | HSOp(0) | Transmitter Lane 0, Differential pair |
| 15 | HSOn(0) | Transmitter Lane 0, differential pair (−) |
| 16 | GND | Ground |
| 17 | PRSNT#2 | Hotplug detect |
| 18 | GND | Ground |
Notes
- A mechanical key between pins 11 and 12 sets the card’s orientation and prevents incorrect insertion; the x1 connector ends at pin 18.
- The table lists the Side B contacts — the side carrying the transmit pair, SMBus, WAKE# and present-detect pins. Side A carries the receiver pair (PERp0/PERn0), the +12 V and +3.3 V rails, the 100 MHz reference clock (REFCLK+/REFCLK−), the PERST# reset and the remaining JTAG pins (TCK/TDI/TDO/TMS).
- HSOp(0)/HSOn(0) (pins 14/15) are the positive and negative halves of the single transmit lane’s differential pair (named PETp0/PETn0 in the specification); pin 15 is the negative half, not a ground.
- Up-plugging: a x1 card fits into a longer x4, x8 or x16 slot.
- PRSNT1# (Side A) and PRSNT#2 (pin 17) form the present-detect loop that lets the system detect the card and support hot-plug.
Signals
- HSOp(0) / HSOn(0) (PETp0/PETn0) — positive and negative halves of the Lane-0 transmit differential pair.
- WAKE# — sideband signal that requests link reactivation from a low-power state.
- SMCLK / SMDAT — System Management Bus (SMBus) clock and data for out-of-band management.
- 3.3Vaux — auxiliary 3.3 V supply, available for wake/management when the main rails are off.
- JTAG1 (TRST#) — JTAG Test Access Port reset; the remaining JTAG pins are on Side A.
- PRSNT#2 — hot-plug present-detect, paired with PRSNT1# on Side A.
- +12v / +3.3v — main power rails.
References
- PCI Express Base Specification, Revision 2.0 (PCI-SIG) — serial-link architecture and per-lane data rates (Internet Archive scan).
- PCI Express Card Electromechanical (CEM) Specification, Revision 3.0 (PCI-SIG) — x1 connector pinout, keying and present-detect.