PCI Express 1x - 36 pin Female Connector
PCI Express was introduced to overcome the limitations of the original PCI bus. Developed and released by Intel over a decade ago, the original PCI bus operated at 33MHz and 32 bits with a peak theoretical bandwidth of 132MB per second. It used a shared bus topology - bus bandwidth is shared among multiple devices - to enable communication among the different devices on the bus.
| Pin |
</center> | <center> Side A Connector </center> |
|—–|——————|———————| | # | Name | Description | | 1 | +12v | +12 volt power | | 2 | +12v | +12 volt power | | 3 | RSVD | Reserved | | 4 | GND | Ground | | 5 | SMCLK | SMBus clock | | 6 | SMDAT | SMBus data | | 7 | GND | Ground | | 8 | +3.3v | +3.3 volt power | | 9 | JTAG1 | +TRST# | | 10 | 3.3Vaux | 3.3v volt power | | 11 | WAKE# | Link Reactivation | || | 12 | RSVD | Reserved | | 13 | GND | Ground | | 14 | HSOp(0) | Transmitter Lane 0, Differential pair | | 15 | HSOn(0) | GND | | 16 | GND | Ground | | 17 | PRSNT#2 | Hotplug detect | | 18 | GND | Ground |
- Intel® Developer Network for PCI Express Architecture (contains a lot of technical documents)
- Ineerfacebus.com: PCI Express Bus Description
- National Instruments: Introduction to PCI Express