The PCI (Peripheral Component Interconnect) Local Bus is a synchronous, parallel expansion-bus standard developed by Intel and formalised by the PCI Special Interest Group (PCI-SIG). The standard connector carries a 32-bit multiplexed address/data bus (AD[31:0]) at a base clock of 33 MHz, with an optional 64-bit extension and optional 66 MHz operation introduced in Revision 2.1 (June 1995); the final conventional-PCI revision, 3.0, was published in August 2002. PCI slots use a card-edge connector with 62 contacts per side (124 total for 32-bit; 188 total for the 64-bit extension segment), keyed at positions 12–13 for 5 V cards and at positions 50–51 for 3.3 V cards; universal cards carry both notches. The bus was the dominant PC expansion interface throughout the 1990s and early 2000s, appearing in desktop PCs, workstations, and servers, and was later succeeded by PCI Express.
PCI = Peripheral Component Interconnect
A bus that runs on schedule
Performance
The PCI local bus was jointly developed by Intel and other industry leaders including IBM in order to bring current and next-generation PCs to new levels of system performance.
The PCI bus is well-equipped to handle newer, more demanding applications. PCI boasts a 32-bit data path, 33 MHz clock speed and a maximum data transfer rate of 132 MB/s. A 64-bit, 66 MHz specification exists for PCI designs. The 64-bit PCI bus doubles data transfer performance to 264 MB/s. The PCI bus includes support for PCI-to-PCI bridge chips, allowing more than three slots. Plug-and-play drivers are configured to determine automatically the level of chip in the system and load the appropriate drivers.
Expandability
The key to PCI technology is that it supplements rather than replaces the traditional I/O bus. PCI is the standard interface bus for high-speed devices, including LANs, SCSI, and video technology. Existing ISA cards work alongside PCI. Most PCI systems support three to five performance-critical peripherals, whether integrated directly onto the motherboard or added through PCI expansion cards such as multimedia, graphics, disk drives, and LAN cards.
How PCI works
PCI is not a true local bus; instead, it occupies an intermediate level between the CPU local bus (processor/memory/cache subsystem) and a standard expansion bus such as ISA. The PCI bus is isolated from the CPU local bus by a PCI bridge/controller. The CPU can write data to PCI peripherals and the bridge/controller can immediately store the data in its buffer, allowing the CPU to proceed to its next operation rather than waiting for the transfer to complete. The buffer then feeds the data to the peripheral at the most efficient rate possible.
PCI also supports bus masters — intelligent devices that, when attached to a system bus, can gain control of the bus and perform tasks independent of the CPU. The CPU can run concurrently with bus-master peripherals, and it can operate independently when a PCI peripheral is active because of its buffered design.
Comparison of bus architectures
| ISA | EISA | VL-Bus | PCI | |
| Data Path Width | 8/16 | 32 | 32/64 | 32/64 |
| Data Bus Speed (MHz) | 5.33/8.33 | 8.33 | 33/50 | 33 |
| Data Transfer Rates (MB/sec) | 5.33/8.33 | 33 | 132/264 | 132/264 |
| Data Rates Implemented (MB/sec) | 5.33/8.33 | 33 | 132 | 132 |
| Number of Slots | 0-8 | 0-8 | 0-2 | 0-4 |
| Bus Masters Supported | No | Yes | Yes | Yes |
| Data/Address Parity | No | No | No | Yes |
| Sync, Channel Checks | No | No | No | Yes |
| Card ID/AutoConfiguration | No | Yes | Yes | Yes |
| Works with ISA/EISA | N/A | N/A | Yes | Yes |
Notes
- The 32-bit PCI connector has 62 contacts per side of the card edge (124 total). The optional 64-bit extension segment adds a further 32 contacts per side (94 total positions per side, 188 contacts in all).
- Keying notches prevent voltage mismatches: the 5 V notch sits at positions 12–13 (56.21 mm from the backplate); the 3.3 V notch sits at positions 50–51 (104.41 mm from the backplate). Universal cards carry both notches and can operate in either slot type.
- The base bus clock is 33 MHz; the optional 66 MHz mode was introduced in PCI Local Bus Specification Revision 2.1 (June 1995).
- The data bus is multiplexed: the same pins carry both address and data (AD[31:0] for 32-bit, AD[63:0] in 64-bit mode), together with C/BE[3:0]# command/byte-enable signals.
- Signalling environments: 5 V and 3.3 V I/O; a 3.3 V auxiliary power rail is also defined.
- Maximum burst transfer rate: 132 MB/s at 32-bit/33 MHz; 264 MB/s at 64-bit/33 MHz; 528 MB/s at 64-bit/66 MHz.
- PCI Local Bus Specification revision history: Rev 2.1 (June 1995), Rev 2.2 (December 1998), Rev 3.0 (August 2002).