96 pin DIN (41612, Type C) 3 rows x 32 pins at the backplane
The Europe Card Bus (ECB) is an 8-bit backplane bus developed informally by Kontron (Germany) from around 1977 and formally specified in 1984, primarily targeting systems built around the Zilog Z80, Intel 8080, and 8085 microprocessors. It uses the 3U Eurocard form factor (100 mm × 160 mm boards) mounted in a 19-inch rack backplane, with a DIN 41612 connector carrying signals on rows A and C (64 pins) for 8-bit operation or all three rows A, B, and C (96 pins) for the extended 16-bit variant. Control signals are Z80-specific, including dedicated lines for memory request, I/O request, bus request/acknowledge, refresh, and the Z80 priority interrupt daisy-chain signals IEI and IEO. Power rails are +5 V, +12 V, −12 V, and −5 V.
Row a (for 8 bit)
| Pin | Name | Description |
|---|---|---|
| a1 + | 5V + | 5 volts dc |
| a2 D | 5 D | ata line bit 5 |
| a3 | D6 | Data line bit 6 |
| a4 | D3 | Data line bit 3 |
| a5 | D4 | Data line bit 4 |
| a6 | A2 | Address 2 |
| a7 | A4 | Address 4 |
| a8 | A5 | Address 5 |
| a9 | A6 | Address 6 |
| a10 | WAIT/ | CPU wait |
| a11 | BUSRQ/ | bus request |
| a12 | ||
| a13 | ||
| a14 | ||
| a15 | ||
| a16 | ||
| a17 | ||
| a18 | A14 | address 14 |
| a19 | ||
| a20 | M1/ | first cycle |
| a21 | ||
| a22 | ||
| a23 | ||
| a24 | ||
| a25 | ||
| a26 | ||
| a27 | IORQ/ | in/out request |
| a28 | RFSH/ | refresh cycle |
| a29 | A13 | address 13 |
| a30 | A9 | address 9 |
| a31 | BUSAK/ | bus acknowledge |
| a32 | GND | signal ground |
Row c (for 8 bit)
| Pin | Name | Description |
|---|---|---|
| c1 | +5V | +5 volts dc |
| c2 | D0 | Data line bit 0 |
| c3 | D7 | Data line bit 7 |
| c4 | D2 | Data line bit 2 |
| c5 | A0 | Address 0 |
| c6 | A3 | Address 3 |
| c7 | A1 | Address 1 |
| c8 | A8 | Address 8 |
| c9 | A7 | Address 7 |
| c10 | ||
| c11 | IEI | interrupt enable in |
| c12 | ||
| c13 | ||
| c14 | D1 | Data line bit 1 |
| c15 | ||
| c16 | IEO | interrupt enable out |
| c17 | A11 | address 11 |
| c18 | A10 | address 10 |
| c19 | ||
| c20 | NMI/ | not maskable interrupt |
| c21 | INT/ | normal interrupt |
| c22 | WR/ | write cycle |
| c23 | ||
| c24 | RD/ | read cycle |
| c25 | HALT/ | cpu stopped |
| c26 | ||
| c27 | A12 | address 12 |
| c28 | A15 | address 15 |
| c29 | ||
| c30 | MREQ/ | memory request |
| c31 | RESET/ | cpu reset |
| c32 | GND | signal ground |
Row b (additional for 16 bit)
| Pin | Name | Description |
|---|---|---|
| b1 | +5V | +5 volts dc |
| b2 | A20 | address 20 |
| b3 | A21 | address 21 |
| b4 | A22 | address 22 |
| b5 | A23 | address 23 |
| b6 | D8 | data line bit 8 |
| b7 | D9 | data line bit 9 |
| b8 | D10 | data line bit 10 |
| b9 | D11 | data line bit 11 |
| b10 | D12 | data line bit 12 |
| b11 | D13 | data line bit 13 |
| b12 | D14 | data line bit 14 |
| b13 | D15 | data line bit 15 |
| b14 | IRQ7 | interrupt 7 |
| b15 | IRQ6 | interrupt 6 |
| b16 | IRQ5 | interrupt 5 |
| b17 | IRQ4 | interrupt 4 |
| b18 | IRQ3 | interrupt 3 |
| b19 | IRQ2 | interrupt 2 |
| b20 | IRQ1 | interrupt 1 |
| b21 | IRQ0 | interrupt 0 |
| b22 | IOWR | I/O write |
| b23 | ?? | ?? |
| b24 | IORC | I/O read |
| b25 | MRDC | Mem read |
| b26 | ?? | ?? |
| b27 | MWRC | Mem write |
| b28 | DS0 | Data Select 0 |
| b29 | DS1 | Data Select 1 |
| b30 | OFF | bus driver tristate |
| b31 | LOCK | bus driver tristate disabled |
| b32 | GND | signal ground |
| DS0 | DS1 | Description |
|---|---|---|
| 0 | 0 | data transfer 16-bit |
| 0 | 1 | only bit 0-7 |
| 1 | 0 | only bit 8-15 |
| 1 | 1 | no data transfer |
Notes
/suffix denotes active-low signals (asserted low).- The 8-bit configuration uses only rows A and C of the DIN 41612 connector (64 pins). Row B pins were intentionally left undefined in this configuration to allow mixing of 64-pin and 96-pin cards in the same backplane without conflict.
- The 16-bit extended variant adds row B (96 pins total), which provides an upper data byte (D8–D15), extended address lines (A20–A23), additional interrupt lines (IRQ0–IRQ7), and separate memory/I/O strobes.
- The ECB bus was formally defined in 1984 by the German company Kontron, though earlier informal use within Kontron systems dates to around 1977. The bus is sometimes referred to as the “Europa Bus” or “Einfach Europaformat Computer Baugruppen.”
- The 8-bit address space covers A0–A15 (16 bits, 64 KB). Some sources list the addressable space as 32 KB (A0–A14 only), depending on variant.
- The Z80 interrupt daisy-chain is implemented via IEI (Interrupt Enable In) and IEO (Interrupt Enable Out), which pass priority from one card to the next along the backplane.
- Pins b23 and b26 in the 16-bit row B extension are unassigned in the available references and remain undocumented.
Signals
Row A and C (8-bit core):
- D0–D7 — 8-bit bidirectional data bus
- A0–A15 — 16-bit address bus (A0–A14 in some variants, yielding 32 KB)
- MREQ/ — Memory Request; asserted by the CPU when the address bus holds a memory address
- IORQ/ — I/O Request; asserted by the CPU during an I/O bus cycle
- RD/ — Read cycle; indicates the CPU or bus master is reading data
- WR/ — Write cycle; indicates the CPU or bus master is writing data
- M1/ — Machine Cycle 1; Z80 signal indicating the first clock cycle of an opcode fetch
- RFSH/ — Refresh; Z80 signal used during DRAM refresh cycles
- HALT/ — CPU has halted and is executing NOP instructions awaiting an interrupt
- WAIT/ — Inserted wait states; asserted by slow peripherals to hold the bus
- BUSRQ/ — Bus Request; asserted by a device requesting control of the bus
- BUSAK/ — Bus Acknowledge; asserted by the CPU granting bus control to the requester
- INT/ — Maskable interrupt request line
- NMI/ — Non-Maskable Interrupt; highest-priority interrupt, cannot be masked
- RESET/ — CPU and system reset
- IEI — Interrupt Enable In; Z80 daisy-chain priority interrupt input
- IEO — Interrupt Enable Out; Z80 daisy-chain priority interrupt output
- PHI — CPU clock input (single-phase); some ECB backplanes also provide a 2PHI signal
- +5V — Primary logic supply voltage
- GND — Signal ground
Row B (16-bit extension):
- D8–D15 — Upper byte of the 16-bit data bus
- A20–A23 — Extended address lines for 24-bit addressing (16 MB space)
- IRQ0–IRQ7 — Interrupt request lines 0–7
- IOWR — I/O Write strobe
- IORC — I/O Read strobe
- MRDC — Memory Read strobe
- MWRC — Memory Write strobe
- DS0, DS1 — Data Select signals controlling 16-bit vs. byte-wide transfers (see table above)
- OFF — Places bus drivers into tristate (high-impedance) mode
- LOCK — Disables bus driver tristate; holds drivers active
References
- Europe Card Bus (ECB) — Z80-family Eurocard bus on DIN 41612 connectors; a de-facto industry standard with no single governing body.