CardBus

CardBus is a 32-bit extension of the PC Card (PCMCIA) interface, introduced in PC Card Standard Release 5.0 (February 1995) and finalised in Release 8.0 (April 2001), published jointly by PCMCIA and JEITA. It uses the same 68-pin card-edge connector as earlier 16-bit PC Cards — two rows of 34 contacts at 1.27 mm (0.050 in) pitch on a card measuring 85.6 mm × 54.0 mm — but operates exclusively at 3.3 V and up to 33 MHz, supporting bus mastering and a theoretical peak throughput of 132 MB/s. CardBus cards are distinguished from 16-bit PCMCIA cards by a shallower keying notch that prevents insertion into 16-bit-only sockets, and by a gold ridge on the card’s dorsal surface. The interface was widely adopted in laptop computers throughout the late 1990s and 2000s before being superseded by ExpressCard.

68 PIN MALE Connector at the controller

68 PIN FEMALE Connector at the peripherals.

Notes

• CardBus operates at 3.3 V only; Vcc on pins 17 and 51 must be 3.3 V. The 16-bit PCMCIA interface supported both 5 V and 3.3 V operation.
• The bus clock (CCLK, pin 19) runs at up to 33 MHz, yielding a peak bandwidth of 132 MB/s with a 32-bit bus.
• CardBus cards carry a shallower keying notch than 16-bit PC Cards, preventing physical insertion into sockets that lack CardBus support. A gold ridge on the dorsal surface further identifies CardBus cards.
• Vpp1 (pin 18) and Vpp2 (pin 52) are optional programming-voltage pins; they carry +12 V if used by flash memory cards, otherwise they may be left unconnected or tied to Vcc.
• CCD1# (pin 36) and CCD2# (pin 67) are card-detect signals; both must be asserted (pulled low through the card) for the host to recognise a card as present.
• The connector pitch is 1.27 mm (0.050 in); card dimensions are 85.6 mm × 54.0 mm for all PC Card types. Thickness varies: Type I = 3.3 mm, Type II = 5.0 mm, Type III = 10.5 mm.
• Release 8.0 of the PC Card Standard added the CardBay interface (supporting USB and IEEE 1394 over the PC Card slot), a 1.8 V Vcore definition, and a redefined Vpp.

Signals

• CAD[31:0] — 32-bit multiplexed address/data bus; address is driven during the address phase and data during subsequent data phases of each transaction.
• CCBE[3:0]# — Command/Byte Enable lines; carry a 4-bit bus command during the address phase and byte-enable qualifiers during data phases, indicating which byte lanes carry valid data.
• CPAR — Parity; even parity across CAD[31:0] and CCBE[3:0]# for error detection.
• CPERR# — Parity Error; asserted by a target to report a data-phase parity error detected on the bus.
• CSERR# — System Error; used to report address-phase parity errors or other critical system errors.
• CFRAME# — Frame; driven by the initiator to indicate the start and duration of a bus transaction; deasserted on the final data phase.
• CIRDY# — Initiator Ready; asserted by the bus master to indicate it is ready to complete the current data phase.
• CTRDY# — Target Ready; asserted by the target to indicate it is ready to complete the current data phase.
• CSTOP# — Stop; asserted by a target to request the initiator to stop the current transaction.
• CDEVSEL# — Device Select; asserted by the target that claims an address during the address phase.
• CBLOCK# — Bus Lock; asserted by the initiator to request an exclusive, uninterruptible bus transaction (atomic read-modify-write sequences). The cell description shows ‘???’ because the signal is named differently in some implementations.
• CREQ# — Request; asserted by a bus-master card to request ownership of the CardBus. Marked ‘???’ in the table; the signal follows the same arbitration convention as REQ# in the PCI Local Bus specification.
• CGNT# — Grant; driven by the host controller to grant the bus to a requesting card master.
• CCLK — Bus Clock; synchronous reference clock for all CardBus transactions, up to 33 MHz.
• CCLKRUN# — Clock Run; allows a card or host to negotiate stopping or slowing the bus clock for power management; active-low open-drain signal.
• CRST# — Reset; host-driven reset forcing all CardBus cards to their initial state.
• CINT# — Interrupt; open-drain interrupt request from card to host.
• CCD1#, CCD2# — Card Detect 1 and 2; both must be low (shorted to GND through the card) for the host to confirm a card is fully seated.
• CVS1, CVS2 — Card Voltage Sense; used by the host to read the card’s voltage requirements before applying Vcc, preventing damage to lower-voltage cards.
• CSTSCHG — Card Status Change; open-drain signal asserted by the card to notify the host of a status change (e.g., write-protect toggle, battery status change). Blank description in the table; described fully in the PC Card Standard electrical specification.
• CAUDIO — Audio; carries audio output from a card (e.g., modem speaker signal) to the host. Marked ‘Audio ???’ in the table as its exact usage is implementation-dependent.
• Vcc (pins 17, 51) — 3.3 V supply voltage to the card.
• Vpp1, Vpp2 (pins 18, 52) — Optional programming voltage; +12 V if used, otherwise may be tied to Vcc or left open.

References

• PC Card Standard Release 8.0, Volume 2: Electrical Specification (April 2001)
• PC Card Standard Release 8.0, Volume 3: Physical Specification (April 2001)

Category:Buses Connectors