Apple Macintosh Portable Processor-Direct Slot (PPDS)

Apple Macintosh - Euro-DIN 96-pin Processor-Direct Slot

The Macintosh Portable Processor-Direct Slot (PPDS) is Apple’s proprietary internal expansion interface introduced with the Macintosh Portable (1989). It uses a 96-pin Euro-DIN connector — the same physical format as the 68000-family PDS fitted to the Macintosh SE — and exposes the 68000 CPU address bus (A1–A23), 16-bit data bus (D0–D15), and a selection of control signals directly to expansion cards. Unlike NuBus, the PDS is model-specific and non-standard across the Macintosh range; the 68000 PDS used in the Portable is electrically incompatible with the 120-pin 68030 PDS used in the SE/30 and II family. A critical constraint of the Portable implementation is its limited power budget: only low-power-consumption expansion cards are supported, as the system cannot supply the current required by most standard PDS peripherals.

Notes

The PPDS uses the same 96-pin Euro-DIN three-row connector (rows A, B, C, 32 pins per row) as the Macintosh SE PDS, but the Portable’s signal assignments differ in several positions and the slot is not electrically interchangeable with the SE. The connector provides direct, unbuffered access to the 68000 CPU bus; expansion cards must therefore observe strict electrical loading limits. Power rails on the Portable PPDS are heavily constrained: the system power budget for expansion cards is very low, and only cards designed for minimal current draw are supported — the Portable cannot supply power to most standard PDS or ADB peripherals. The +5/3.7V and +5/0V pins reflect the Portable’s sleep-mode power management; card designs must tolerate both voltage states. The /SYS.PWR signal allows the Power Manager to instruct expansion logic to tri-state its outputs and enter an idle state during sleep. The 16M clock is the 68000 system clock reference for the Portable.

Signals

• D0-D15 — Unbuffered 16-bit data bus, bits 0 through 15
• A1-A23 — Unbuffered address bus, bits 1 through 23 (A0 is implied by /UDS and /LDS)
• 16M — 16 MHz system clock derived from the Portable’s main oscillator
• /EXT.DTACK — External data transfer acknowledge input to the processor glue logic; assertion delays generation of the internal /DTACK signal, allowing slow peripherals to insert wait states
• E — 6800-compatibility E (enable) clock, derived from the 68000 clock
• /BERR — Bus error; asserted by system logic when /AS remains low for longer than approximately 250 µs, indicating a bus timeout
• /IPL0-/IPL2 — Interrupt priority level inputs 0 through 2; encode the highest-priority pending interrupt for the 68000
• /SYS.RST — System reset; assertion initiates a full hardware reset
• /SYS.PWR — Power Manager control signal; when asserted, instructs expansion circuits to tri-state their outputs and enter an idle state; deasserted (pulled high) during normal operation and sleep
• /AS — Address strobe; indicates a valid address is present on the address bus
• /UDS — Upper data strobe; selects the high byte (D8–D15) of the data bus
• /LDS — Lower data strobe; selects the low byte (D0–D7) of the data bus
• R/W — Read/write direction signal; high = read, low = write
• /DTACK — Data transfer acknowledge; asserted by the addressed device to complete a bus cycle
• /DELAY.CS — Wait-state indicator; signals that an additional wait state has been inserted into the current memory cycle, permitting the card to delay its chip-select assertion
• /BG — Bus grant; asserted by the 68000 in response to a bus request, granting mastership of the bus
• /BGACK — Bus grant acknowledge; asserted by the device that has taken bus mastership
• /BR — Bus request; asserted by an expansion device to request control of the system bus
• /VMA — Valid memory address; 6800-compatibility signal indicating a valid synchronous bus cycle
• /VPA — Valid peripheral address; asserted to indicate that the addressed device is a 6800-family peripheral requiring synchronous (E-clock) operation
• FC0-FC2 — Function code outputs from the 68000 encoding the address space type (user/supervisor, data/program) of the current bus cycle
• +5/0V — Supplies +5 V during normal operation; drops to 0 V when the system enters sleep mode
• +5/3.7V — Supplies +5 V during normal operation; drops to approximately 3.7 V during sleep mode to maintain state in certain circuits

References

• Guide to the Macintosh Family Hardware, Second Edition — Apple Computer, Inc. / Addison-Wesley, 1990 (Chapter 14, Tables 14-1 and 14-3: 96-pin 68000 PDS signal definitions for the Macintosh SE and Portable)

Category:Buses Connectors