25 PIN D-SUB MALE at the computer
The PC serial port in its full 25-pin form implements the EIA/TIA-232 (RS-232) standard, first introduced in 1962 and most recently revised to TIA-232-F in October 1997. The 25-position D-sub connector is specified by ISO 2110, with the DTE (computer) side presenting a female housing with male pins and the DCE (modem) side presenting a male housing with female pins. Signal logic uses unbalanced single-ended signalling per ITU-T V.28, with driver outputs of ±5 V to ±15 V, receiver thresholds at ±3 V, a maximum data rate of 20 kbit/s, and a maximum cable capacitance of 2500 pF. In practice, PC manufacturers moved to the compact 9-pin DE-9 connector defined by TIA/EIA-574, leaving many of the 25 pins unused in common PC applications.
| Pin | Name | Dir | Description |
|---|---|---|---|
| 1 | SHIELD | - | Shield Ground |
| 2 | TXD | OUT | Transmit Data |
| 3 | RXD | IN | Receive Data |
| 4 | RTS | OUT | Request to Send |
| 5 | CTS | IN | Clear to Send |
| 6 | DSR | IN | Data Set Ready |
| 7 | GND | - | System Ground |
| 8 | CD | IN | Carrier Detect |
| 9 | n/c | - | |
| 10 | n/c | - | |
| 11 | n/c | - | |
| 12 | n/c | - | |
| 13 | n/c | - | |
| 14 | n/c | - | |
| 15 | n/c | - | |
| 16 | n/c | - | |
| 17 | n/c | - | |
| 18 | n/c | - | |
| 19 | n/c | - | |
| 20 | DTR | OUT | Data Terminal Ready |
| 21 | n/c | - | |
| 22 | RI | IN | Ring Indicator |
| 23 | n/c | - | |
| 24 | n/c | - | |
| 25 | n/c | - |
Signals
- SHIELD — Chassis or cable shield ground; must not be connected to Signal Ground (pin 7) at the connector.
- TXD — Transmitted Data (V.24 circuit 103): serial data sent by the DTE to the DCE; logic 1 (MARK) is a negative voltage, logic 0 (SPACE) is positive per V.28.
- RXD — Received Data (V.24 circuit 104): serial data received by the DTE from the DCE.
- RTS — Request to Send (V.24 circuit 105): asserted by the DTE to request the DCE to prepare for transmission.
- CTS — Clear to Send (V.24 circuit 106): asserted by the DCE to indicate it is ready to accept data from the DTE; used for hardware flow control together with RTS.
- DSR — Data Set Ready (V.24 circuit 107): indicates the DCE is powered on and ready.
- GND — Signal Ground (V.24 circuit 102): reference for all electrical signals; separate from the shield ground on pin 1.
- CD — Carrier Detect / Received Line Signal Detector (V.24 circuit 109): asserted by the DCE when a valid carrier is detected on the line.
- DTR — Data Terminal Ready (V.24 circuit 108): asserted by the DTE to indicate it is ready to communicate; used to instruct the DCE to connect or remain connected to the line.
- RI — Ring Indicator (V.24 circuit 125): asserted by the DCE when an incoming ring signal is detected on the telephone line.
Notes
- Direction is DTE (Computer) relative DCE (Modem).
- Do not connect SHIELD (pin 1) to GND (pin 7); the shield should be bonded to chassis earth, not signal ground.
- The ISO 2110 25-pin D-sub is the mechanically specified connector for RS-232; the DTE connector is a female housing with male pins, and the DCE connector is a male housing with female pins.
- Most PC implementations only populate the 9 signals shown above. The remaining pins (9–19, 21, 23–25) are not connected in standard PC serial port use, though the full TIA-232-F standard defines additional timing and secondary-channel circuits for those positions.
- The maximum specified data rate is 20 kbit/s and the cable capacitance limit is 2500 pF; exceeding the capacitance limit reduces effective data rate and increases bit error rate.
- For synchronous DTE/DCE applications requiring the full 25-pin circuit set (including timing circuits on pins 15, 17, and 24), the EIA-530 standard provides an RS-422-based alternative on the same DB-25 connector at data rates from 20 kbit/s to 2 Mbit/s.
References
- Fundamentals of RS-232 Serial Communications
- AN-917: Popular Connector Pin Assignments for Data Communications
- ITU-T Recommendation V.24: List of Definitions for Interchange Circuits Between DTE and DCE
- ITU-T Recommendation V.28: Electrical Characteristics for Unbalanced Double-Current Interchange Circuits