DRAM SIMM ECC 72 Pin

72 pin SIMM DRAM

The 72-pin ECC SIMM (Single Inline Memory Module) is a DRAM module format standardised under JEDEC JESD21-C, Section 4.4.2, and was widely deployed in workstations and servers from approximately 1992 to 1998. It provides a 36-bit or 40-bit wide data path — 32 data bits augmented by four or eight Error Correcting Code (ECC) bits — distinguishing it from the pin-incompatible standard non-ECC 72-pin SIMM. Both 5.0 V and 3.3 V variants are defined; a voltage key in the socket prevents accidental interchange. Supported DRAM technologies include Fast Page Mode (FPM) and Extended Data-Out (EDO), in capacities from 256 Kword to 512 Mword.

• SIMM = Single Inline Memory Module
• DRAM = Dynamic Random Access Memory
• ECC = Error Correcting Code

Signals

• DQ0–DQ31 — 32-bit bidirectional data bus; driven and sampled by the memory controller during read and write cycles.
• DQ32–DQ35 — ECC check-bit lines (CB0–CB3 in JEDEC notation); present on both x36 and x40 ECC modules.
• DQ36–DQ39 — Additional ECC or extended data bits; populated on the x40 “Optimised” variant only; n/c on the standard x36 ECC module (pins 64, 65, 66, 71).
• /ECC (pin 48) — ECC enable/control signal; wiring differs from the non-ECC module and contributes to the pin incompatibility between the two sub-families.
• A0–A11 — Multiplexed row/column address bus; row address is latched on the falling edge of /RAS, column address on the falling edge of /CAS.
• /RAS0, /RAS1 — Row Address Strobe signals; two signals support double-sided or banked module configurations.
• /CAS0, /CAS1 — Column Address Strobe signals; each /CAS selects a byte lane within the 32-bit data path.
• /WE — Write Enable; low selects a write cycle, high selects a read cycle.
• PD1–PD5 — Presence Detect pins; a resistor network on the module connects these pins to encode capacity, speed grade, and module type (including ECC identification) to the system board.
• VCC (pins 10, 30, 59) — +5 V supply (5.0 V modules) or +3.3 V supply (3.3 V modules); the voltage key prevents a 3.3 V module being inserted into a 5.0 V socket.
• VSS (pins 1, 39, 72) — Ground reference.

Notes

• The ECC 72-pin SIMM is defined separately from the standard 72-pin SIMM in JEDEC JESD21-C, Section 4.4.2 (Figure 4.4.2-3A); the two sub-families are similar in appearance but are NOT pin-compatible.
• A voltage key notch in the module PCB edge differentiates 5.0 V and 3.3 V variants; sockets are keyed to prevent incorrect insertion.
• The Presence Detect (PD) coding on an ECC module explicitly identifies it as ECC, allowing the host system to enable or disable ECC logic accordingly.
• Single-sided and double-sided configurations are supported, using 1 M, 4 M, 16 M, 64 M, or 256 M DRAM devices.
• Supported access modes include Fast Page Mode (FPM), Extended Data-Out (EDO), refresh via RAS-only, CAS-before-RAS (CBR), and hidden refresh.

References

• JEDEC Standard No. 21-C, Section 4.4.2 — 72 Pin SIMM DRAM Module Family
• 72-Pin SIMM Datasheet — Micron Technology 4 Meg x 32 and 8 Meg x 32 DRAM SIMMs

Category:Memory Connectors