DIMM DRAM 168 Pin

168-pin SDRAM DIMM

• DIMM = Dual Inline Memory Module
• DRAM = Dynamic Random Access Memory, Synchronous to Positive Clock Edge

The 168-pin SDRAM DIMM is standardised under JEDEC JESD21-C (mechanical outline MO-161) and was the dominant desktop memory form factor from the mid-1990s through the early 2000s. It carries a 64-bit data bus (or 72-bit with ECC check bits CB0–CB7), operates at 3.3 V with LVTTL-compatible signalling, and runs synchronously on the positive edge of the system clock at either 100 MHz (PC100) or 133 MHz (PC133). Both unbuffered (UDIMM) and registered (RDIMM) variants share the same 168-pin, 1.27 mm pitch edge connector; a Serial Presence Detect (SPD) EEPROM accessed via I²C on pins 82–83 and 164–166 allows the host to auto-configure timing parameters.

The 168-pin DIMM has 84 pins per PWB side. The front side contains left-side pins 1–42 and right-side pins 43–84. The back side has left-side pins 85–126 and right-side pins 127–168.

PIN CONFIGURATIONS (Front side / back side)

Notes

• The connector is a 168-pin dual-sided edge connector with 1.27 mm (50 mil) contact pitch and a PCB body width of 133.35 mm, as defined by JEDEC mechanical outline MO-161.
• A notch (key) in the PCB edge prevents insertion of a 3.3 V DIMM into a 5 V socket and vice versa; a second notch differentiates buffered from unbuffered modules.
• Unbuffered DIMMs (UDIMMs) connect address, command, and clock lines directly to the SDRAM devices and are used in consumer desktops and workstations. Registered DIMMs (RDIMMs) pass those signals through a register/buffer and a PLL clock driver, reducing bus loading in server platforms.
• Non-ECC modules use a 64-bit data bus (DQ0–DQ63); ECC modules extend this to 72 bits by adding check bits CB0–CB7.
• Address pins A10–A13 are NC on smaller-capacity modules; their presence depends on the DRAM row-address depth used.
• Pins marked RFU (Reserved for Future Use) must be left unconnected on the motherboard; NC pins are not connected on that specific module configuration but may carry signals in other configurations.

Signals

• VDD — +3.3 V power supply
• VSS — Ground
• DQ0–DQ63 — 64-bit bidirectional data bus; all signals are LVTTL-compatible and synchronous to the clock
• CB0–CB7 — Check-bit (ECC) data lines; NC on non-ECC 64-bit modules, active on 72-bit ECC modules
• A0–A13 — Multiplexed row/column address bus; strobed by RAS# and CAS# respectively; higher address lines are NC on lower-density devices
• BA0–BA1 — Bank address select inputs
• CAS0#–CAS7# — Column Address Strobe, active-low; one signal per byte lane; selects the target rank/byte during a memory access
• RAS0#, RAS2# — Row Address Strobe, active-low; one per rank pair
• WE0#, WE2# — Write Enable, active-low; combined with RAS#/CAS# to define the command cycle
• OE0#, OE2# — Output Enable, active-low; controls data-output drivers for each rank pair
• CK0–CK3 — Differential clock inputs (positive half); all SDRAM operations are registered on the rising edge
• SDA — I²C serial data line for the SPD EEPROM (pin 82)
• SCL — I²C serial clock line for the SPD EEPROM (pin 83)
• SA0–SA2 — SPD EEPROM I²C address select lines (pins 165–167); set the device address on the I²C bus
• WP — Write-protect input for the SPD EEPROM; not shown in this table but defined in the Intel unbuffered DIMM specification
• NC — No connect on this module configuration
• RFU — Reserved for Future Use; must not be connected

References

• PC SDRAM Unbuffered DIMM Specification, Revision 1.0 (Intel, February 1998)
• PC133 SDRAM Registered DIMM Design Specification, Revision 1.1 (IBM / Reliance Computer Corporation, August 1999)
• Micron MT4LSDT464A / MT4LSDT864A / MT4LSDT1664A — 168-Pin SDRAM UDIMM Datasheet
• Micron MT8LSDT1664A / MT16LSDT3264A — 168-Pin SDRAM UDIMM Datasheet
• Micron MT18LSDT6472 — 168-Pin SDRAM RDIMM (ECC) Datasheet

Category:Memory Connectors