DRAM SIMM 72 Pin

The 72-pin DRAM SIMM memory module (FPM/EDO): 32-bit pinout, presence-detect pins, keying and signals, as used in 486 and Pentium-era PCs and Macs.

Updated:

72 pin SIMM DRAM 72 pin SIMM DRAM

  • SIMM = Single Inline Memory Module
  • DRAM = Dynamic Random Access Memory

The 72-pin SIMM presents a 32-bit data path (36 bits with parity) and was the standard main-memory module for 486 and early Pentium PCs and contemporary Macintoshes, roughly 1993–1998. It superseded the 8-bit 30-pin SIMM — a single 72-pin module fills a 486’s 32-bit memory bank, where four 30-pin modules were previously needed — and was itself replaced by the 64-bit 168-pin DIMM. Modules were made in Fast Page Mode (FPM) and Extended Data Out (EDO) versions on the same connector, mostly at 5 V. The pinout is defined by JEDEC Standard 21-C.

PINSYMBOLPINSYMBOLPINSYMBOLPINSYMBOL
1Vss19A1037NC55DQ12
2DQ120DQ538NC56DQ28
3DQ1721DQ2139Vss57DQ13
4DQ222DQ640CAS0#58DQ29
5DQ1823DQ2241CAS2#59Vdd
6DQ324DQ742CAS3#60DQ30
7DQ1925DQ2343CAS1#61DQ14
8DQ426DQ844RAS0#62DQ31
9DQ2027DQ2445NC/RAS1#*63DQ15
10VDD28A746NC64DQ32
11NC29NC (A11)47WE#65DQ16
12A030VDD48NC66NC
13A131A849DQ967PRD1
14A232A950DQ2568PRD2
15A333NC/RAS3#*51DQ1069PRD3
16A434RAS2#52DQ2670PRD4
17A535NC53DQ1171NC
18A636NC54DQ2772Vss

(*) 32MB version only.

Notes

  • Keying. A polarising notch at the centre of the card edge (between pins 36 and 37) prevents reversed insertion, and a voltage key distinguishes 5 V from 3.3 V sockets. The module is inserted at an angle and clipped upright.
  • Presence detect. Pins 67–70 (PRD1–PRD4, also called PD1–PD4) are strap pins — each tied to Vss or left open — that encode the module’s capacity and speed grade so the system can configure itself automatically.
  • Second-bank strobes. RAS1# (pin 45) and RAS3# (pin 33) drive a second internal bank and are populated only on double-sided modules (the “32 MB version” in the table); single-bank modules leave them unconnected.
  • Data width. One 72-pin SIMM forms a complete 32-bit bank on a 486; on a 64-bit Pentium bus, two matched modules are fitted per bank. Parity modules add four bits (36-bit), and ECC modules use a related 39-bit layout.
  • JEDEC names the strobes RE#/CE# (Row/Column Enable) and the write line W#, but manufacturer datasheets and this table use the older RAS#/CAS#/WE# names for the same pins.

Signals

  • A0–A11 — multiplexed row/column address inputs; the high-order lines are unused on smaller-capacity modules.
  • DQ1–DQ32 — bidirectional 32-bit data bus (DQ33–DQ36 add byte parity on parity modules).
  • RAS0#–RAS3# — active-low Row Address Strobes; RAS1#/RAS3# serve the second bank on double-sided modules.
  • CAS0#–CAS3# — active-low byte Column Address Strobes, one per data byte for individual byte writes.
  • WE# — active-low Write Enable.
  • PRD1–PRD4 — presence-detect straps encoding capacity and speed.
  • Vdd / Vss — +5 V supply and ground.

References

Category:Memory Connectors