30 PIN SIMM DRAM
- SIMM = Single Inline Memory Module
- DRAM = Dynamic Random Access Memory
The 30-pin SIMM is a JEDEC-standardised memory module providing an 8-bit data bus (9-bit with optional parity) and operating from a single +5 V supply. It uses Fast Page Mode (FPM) DRAM and supports capacities from 256 KB to 4 MB per module, with refresh accomplished via RAS-only, CAS-before-RAS (CBR), or hidden-refresh cycles. Introduced around 1986, it was the dominant desktop memory format through the early 1990s, used in IBM-compatible PCs, Apple Macintosh systems, and workstations before being superseded by the 72-pin SIMM around 1993.
| Pin | Name | Description |
|---|---|---|
| 1 | VCC | +5 VDC |
| 2 | /CAS | Column Address Strobe |
| 3 | DQ0 | Data 0 |
| 4 | A0 | Address 0 |
| 5 | A1 | Address 1 |
| 6 | DQ1 | Data 1 |
| 7 | A2 | Address 2 |
| 8 | A3 | Address 3 |
| 9 | GND | Ground |
| 10 | DQ2 | Data 2 |
| 11 | A4 | Address 4 |
| 12 | A5 | Address 5 |
| 13 | DQ3 | Data 3 |
| 14 | A6 | Address 6 |
| 15 | A7 | Address 7 |
| 16 | DQ4 | Data 4 |
| 17 | A8 | Address 8 |
| 18 | A9 | Address 9 |
| 19 | A10 | Address 10 |
| 20 | DQ5 | Data 5 |
| 21 | /WE | Write Enable |
| 22 | GND | Ground |
| 23 | DQ6 | Data 6 |
| 24 | A11 | Address 11 |
| 25 | DQ7 | Data 7 |
| 26 | QP | Data Parity Out |
| 27 | /RAS | Row Address Strobe |
| 28 | /CASP | /CAS line for the parity RAM on the card * |
| 29 | DP | Data Parity In |
| 30 | VCC | +5 VDC |
Signals
- VCC — +5 V supply (pins 1 and 30); tolerance ±10 %.
- /CAS — Column Address Strobe; latches the column portion of the multiplexed row/column address on the falling edge.
- DQ0–DQ7 — Bidirectional 8-bit data bus; TTL-compatible inputs and outputs.
- A0–A11 — Multiplexed row/column address inputs; not all lines are active on every module capacity (see Notes).
- GND — Ground reference (pins 9 and 22).
- /WE — Write Enable; selects a read or write cycle.
- /RAS — Row Address Strobe; latches the row address and initiates an access cycle.
- QP — Data Parity Output; driven by the parity DRAM on parity-equipped modules. Not connected (N/C) on non-parity modules.
- DP — Data Parity Input; carries the expected parity bit from the host for write operations. N/C on non-parity modules.
- /CASP — Separate Column Address Strobe for the parity DRAM chip (*); see Notes. N/C on non-parity modules.
Notes
- (*) Parity motherboards required additional time to generate a parity bit, so the CAS signal for the parity DRAM had to be controlled separately from the main /CAS line — hence the dedicated /CASP pin.
- QP, DP, and /CASP are N/C on SIMMs without parity. The module shown is a 4 MB × 9 (parity) configuration.
- Address line usage varies with capacity: A9 is N/C on 256 KB modules; A10 is N/C on 256 KB and 1 MB modules; A11 is N/C on 256 KB, 1 MB, and 4 MB modules.
- Speed options include 60 ns access / 110 ns cycle (−6) and 70 ns access / 130 ns cycle (−7).
- All signals are TTL-compatible; standby power consumption is typically around 6 mW, rising to approximately 450 mW active.