DRAM SIMM 30 Pin

It appears that you are using AdBlocking software. The cost of running this website is covered by advertisements. If you like it please feel free to a small amount of money to secure the future of this website.

30 PIN SIMM DRAM 30 PIN SIMM DRAM

  • SIMM = Single Inline Memory Module
  • DRAM = Dynamic Random Access Memory
Pin Name Description
1 VCC +5 VDC
2 /CAS Column Address Strobe
3 DQ0 Data 0
4 A0 Address 0
5 A1 Address 1
6 DQ1 Data 1
7 A2 Address 2
8 A3 Address 3
9 GND Ground
10 DQ2 Data 2
11 A4 Address 4
12 A5 Address 5
13 DQ3 Data 3
14 A6 Address 6
15 A7 Address 7
16 DQ4 Data 4
17 A8 Address 8
18 A9 Address 9
19 A10 Address 10
20 DQ5 Data 5
21 /WE Write Enable
22 GND Ground
23 DQ6 Data 6
24 A11 Address 11
25 DQ7 Data 7
26 QP Data Parity Out
27 /RAS Row Address Strobe
28 /CASP /CAS line for the parity RAM on the card *
29 DP Data Parity In
30 VCC +5 VDC

Notes

  • (*) The parity generator circuitry of the motherboards needed a longer time to generate a parity bit, so the CAS for the extra DRAM had be controlled seperately, hence, the extra /CAS line. (Tom Walsh).
  • The line is the /CAS line for the parity RAM on the card. The parity generator circuitry of the motherboards needed a longer time to generate a parity bit, so the CAS for the extra DRAM had be controlled seperately, hence, the extra /CAS line.
  • SIMM above is a 4MBx9.
  • QP & DP is N/C on SIMMs without parity.
  • A9 is N/C on 256kB.
  • A10 is N/C on 256kB & 1MB. A11 is N/C on 256kB, 1MB & 4MB.

References

Category:Memory Connectors

 

© 1998-2017 – Nicola Asuni - Tecnick.com - All rights reserved.
about - disclaimer - privacy