168-pin SDRAM DIMM
- DIMM: Dual Inline Memory Module
- SDRAM: Synchronous Dynamic Random Access Memory, Synchronous to Positive Clock Edge.
The 168-pin DIMM is the standard SDRAM main-memory module of late-1990s and early-2000s PCs (PC66/PC100/PC133). It carries a 64-bit data path (72-bit with ECC) at 3.3 V and runs synchronously to the system clock. A single module fills a Pentium-class 64-bit memory bank, where two 72-pin SIMMs were previously needed. JEDEC standardised the pinout, and the module was succeeded by the 184-pin DDR DIMM.
The 168-pin DIMM have 84 pins per PWB side. The Front Side board pinout contains left side pins 1-42, and right side pins 43-84. The Back Side board pinout has left side pins 85-126, and right side pins 127-168.
PIN CONFIGURATIONS (Front side / back side)
| Pin# | Front Side | Pin# | Front Side | Pin# | Back Side | Pin# | Back Side |
|---|---|---|---|---|---|---|---|
| 1 | VSS | 43 | VSS | 85 | VSS | 127 | VSS |
| 2 | DQ0 | 44 | NC | 86 | DQ32 | 128 | CKE0 |
| 3 | DQ1 | 45 | /S2 | 87 | DQ33 | 129 | /S3 |
| 4 | DQ2 | 46 | DQMB2 | 88 | DQ34 | 130 | DQMB6 |
| 5 | DQ3 | 47 | DQMB3 | 89 | DQ35 | 131 | DQMB7 |
| 6 | VCC | 48 | NC | 90 | VCC | 132 | A13 |
| 7 | DQ4 | 49 | VCC | 91 | DQ36 | 133 | VCC |
| 8 | DQ5 | 50 | NC | 92 | DQ37 | 134 | NC |
| 9 | DQ6 | 51 | NC | 93 | DQ38 | 135 | NC |
| 10 | DQ7 | 52 | CB2 | 94 | DQ39 | 136 | CB6 |
| 11 | DQ8 | 53 | CB3 | 95 | DQ40 | 137 | CB7 |
| 12 | VSS | 54 | VSS | 96 | VSS | 138 | VSS |
| 13 | DQ9 | 55 | DQ16 | 97 | DQ41 | 139 | DQ48 |
| 14 | DQ10 | 56 | DQ17 | 98 | DQ42 | 140 | DQ49 |
| 15 | DQ11 | 57 | DQ18 | 99 | DQ43 | 141 | DQ50 |
| 16 | DQ12 | 58 | DQ19 | 100 | DQ44 | 142 | DQ51 |
| 17 | DQ13 | 59 | VCC | 101 | DQ45 | 143 | VCC |
| 18 | VCC | 60 | DQ20 | 102 | VCC | 144 | DQ52 |
| 19 | DQ14 | 61 | NC | 103 | DQ46 | 145 | NC |
| 20 | DQ15 | 62 | NC | 104 | DQ47 | 146 | NC |
| 21 | CB0 | 63 | CKE1 | 105 | CB4 | 147 | NC |
| 22 | CB1 | 64 | VSS | 106 | CB5 | 148 | VSS |
| 23 | VSS | 65 | DQ21 | 107 | VSS | 149 | DQ53 |
| 24 | NC | 66 | DQ22 | 108 | NC | 150 | DQ54 |
| 25 | NC | 67 | DQ23 | 109 | NC | 151 | DQ55 |
| 26 | VCC | 68 | VSS | 110 | VCC | 152 | VSS |
| 27 | /WE0 | 69 | DQ24 | 111 | /CAS | 153 | DQ56 |
| 28 | DQMB0 | 70 | DQ25 | 112 | DQMB4 | 154 | DQ57 |
| 29 | DQMB1 | 71 | DQ26 | 113 | DQMB5 | 155 | DQ58 |
| 30 | /S0 | 72 | DQ27 | 114 | /S1 | 156 | DQ59 |
| 31 | NC | 73 | VCC | 115 | /RAS | 157 | VCC |
| 32 | VSS | 74 | DQ28 | 116 | VSS | 158 | DQ60 |
| 33 | A0 | 75 | DQ29 | 117 | A1 | 159 | DQ61 |
| 34 | A2 | 76 | DQ30 | 118 | A3 | 160 | DQ62 |
| 35 | A4 | 77 | DQ31 | 119 | A5 | 161 | DQ63 |
| 36 | A6 | 78 | VSS | 120 | A7 | 162 | VSS |
| 37 | A8 | 79 | CK2 | 121 | A9 | 163 | CK3 |
| 38 | A10/(AP) | 80 | NC | 122 | BA0 | 164 | NC |
| 39 | BA1 | 81 | WP | 123 | A11 | 165 | SA0 |
| 40 | VCC | 82 | SDA | 124 | VCC | 166 | SA1 |
| 41 | VCC | 83 | SCL | 125 | CK1 | 167 | SA2 |
| 42 | CK0 | 84 | VCC | 126 | A12 | 168 | VCC |
Notes
- Keying. Two notches in the contact edge encode the module type and voltage: one between pins 10 and 11 marks an unbuffered module, and one centred between pins 40 and 41 marks 3.3 V signalling. A registered/buffered module has its type notch in a different position, so it cannot be fitted in an unbuffered socket. Contact pitch is 1.27 mm (0.05 in).
- Serial Presence Detect. A small I²C EEPROM (read on SDA/SCL, addressed by SA0–SA2, write-protected by WP) holds the module’s organisation and timing so the BIOS can configure it automatically.
- ECC. The eight check-bit lines CB0–CB7 carry error-correction bits on 72-bit modules; they are not connected on plain 64-bit modules.
- Width. One 168-pin DIMM provides a complete 64-bit data path. Unbuffered modules drive the SDRAMs directly; registered modules re-drive command and address through a register and PLL for heavier loading.
Signals
- DQ0–DQ63 — bidirectional 64-bit data bus.
- CB0–CB7 — ECC check bits (72-bit modules only).
- A0–A13, BA0/BA1 — multiplexed row/column address and bank-address inputs (A10/AP doubles as auto-precharge).
- /S0–/S3 — chip selects, one per physical row of SDRAMs.
- DQMB0–DQMB7 — byte data masks.
- /RAS, /CAS, /WE0 — row-address-strobe, column-address-strobe and write-enable command inputs.
- CK0–CK3, CKE0/CKE1 — clock inputs and clock enables.
- SDA / SCL / SA0–SA2 / WP — serial presence-detect EEPROM data, clock, address and write-protect.
- VDD / VSS — +3.3 V supply and ground.
References
- Intel PC SDRAM Unbuffered DIMM Specification, Rev 1.0 (1998) — the 168-pin connector pinout, the two-notch keying and the SPD interface.
- Micron 168-pin SDRAM UDIMM datasheet (MT8/16LSDTxx64A) — PC100/PC133 unbuffered module, signal set and front/back pin split.