MSX Expansion

50-pin cartridge/expansion bus connector defined by ASCII Corporation and Microsoft for the MSX standard (1983–), carrying the full Z80 system bus at TTL levels.

Updated:

MSX expansion, 50-pin edge

50 PIN Connector at the Computer.

The MSX cartridge and expansion slot is a 50-pin connector defined in the MSX standard, which was jointly developed by ASCII Corporation and Microsoft Corporation in 1983–1984 and governs all MSX-compatible home computers produced from 1983 onwards. It exposes the complete Z80 system bus — a 16-bit address bus (A0–A15), an 8-bit bidirectional data bus (D0–D7), and the full set of Z80 control signals — along with hardware-decoded chip-select lines that relieve cartridges of address decoding. The connector uses a 2.54 mm (0.1-inch) pitch 50-pin header; all signals are TTL-level compatible. The MSX2 standard (1985) retained the identical 50-pin electrical specification, giving MSX2 machines full backward compatibility with MSX1 cartridges.

PinNameDirDescription
1/CS1OUTMemory Read in addresses 4000-7FFF
2/CS2OUTMemory Read in addresses 8000-BFFF
3/CS12OUTMemory Read in addresses 4000-BFFF
4/SLTSLOUTLow when Slot 2 (cartridge slot) is selected
5n/c-Not connected.
6/RFSHOUTRefresh signal from CPU
7/WAITINOC, Tells CPU to wait. Refresh signal is not maintained
8/INTINOC, Requests a interrupt to CPU (call to addr 38h)
9/M1OUTCPU fetches first part of instruction from memory.
10/BUSDIRINNC, was used to control the data direction.
11/IORQOUTI/O request signal. (Address=Port)
12/MREQOUTMemory request signal. (Address=Address)
13/WROUTWrite signal (strobe)
14/RDOUTRead signal (strobe)
15/RESETINReset
16n/c-Not connected.
17A0OUTAddress 0
18A1OUTAddress 1
19A2OUTAddress 2
20A3OUTAddress 3
21A4OUTAddress 4
22A5OUTAddress 5
23A6OUTAddress 6
24A7OUTAddress 7
25A8OUTAddress 8
26A9OUTAddress 9
27A10OUTAddress 10
28A11OUTAddress 11
29A12OUTAddress 12
30A13OUTAddress 13
31A14OUTAddress 14
32A15OUTAddress 15
33D0IN/OUTData 0
34D1IN/OUTData 1
35D2IN/OUTData 2
36D3IN/OUTData 3
37D4IN/OUTData 4
38D5IN/OUTData 5
39D6IN/OUTData 6
40D7IN/OUTData 7
41GND——Ground
42CLOCKOUTCPU clock, 3.579 MHz
43GND——Ground
44SW1-NC, Insert/remove detection for protection
45+5VOUT+5 VDC (300mA max /slot)
46SW2-NC, Insert/remove detection for protection
47+5VOUT+5 VDC (300mA max /slot)
48+12VOUT+12 VDC (50mA max /slot)
49SOUNDININSound input (-5dBm)
50-12VOUT-12 VDC (50mA max /slot)

Notes

  • Direction is Computer relative Peripheral.
  • The connector is a 50-pin 2.54 mm pitch header. Plug-in cartridges use a PCB edge connector; expansion boxes commonly use a 50-pin IDC header with one or two polarising keys.
  • /WAIT (pin 7) and /INT (pin 8) are open-collector lines; cartridges asserting these must use an open-collector or open-drain driver and must not drive them high actively.
  • /CS1, /CS2, and /CS12 are hardware-decoded chip-select outputs from the system board, removing the need for cartridges to decode the address bus independently.
  • Slot selection is managed in software via the Z80 8255 PPI at I/O port A8h (basic slots 0–3). An expanded slot register at memory address FFFFh allows each primary slot to be subdivided into four sub-slots, yielding up to 16 logical slots.
  • The +12 V (pin 48) and −12 V (pin 50) rails share a combined 50 mA budget across all slots; the +5 V rails (pins 45, 47) each supply up to 300 mA per slot.
  • CLOCK (pin 42) runs at 3.579545 MHz, the NTSC colour sub-carrier frequency, and is available to cartridges without a separate oscillator.
  • SOUNDIN (pin 49) at −5 dBm nominal allows cartridges such as FM-sound and wave-table sound expansion boards to feed audio directly into the system’s amplifier mix.
  • Pins 5 and 16 are reserved and not connected in the original MSX standard.

Signals

  • /CS1 — active-low chip select asserted by the system when the CPU addresses the range 4000h–7FFFh in the selected slot.
  • /CS2 — active-low chip select for the range 8000h–BFFFh in the selected slot.
  • /CS12 — active-low chip select spanning 4000h–BFFFh; intended for 256 KB ROM cartridges covering both ranges.
  • /SLTSL — active-low slot-select output; goes low when this particular slot is the currently addressed slot.
  • /RFSH — Z80 DRAM refresh signal; asserted by the CPU during the refresh cycle.
  • /WAIT — open-collector input to the CPU; a cartridge holds this line low to extend the bus cycle until it is ready.
  • /INT — open-collector maskable interrupt request; a cartridge asserts this to request a CPU interrupt, vectored to address 38h in IM 1.
  • /M1 — asserted by the CPU during the first machine cycle (opcode fetch) of each instruction.
  • /BUSDIR — bus-direction control; not connected in most MSX implementations.
  • /IORQ — active-low I/O request; asserted when the CPU is performing an I/O port read or write (address bus carries port number).
  • /MREQ — active-low memory request; asserted when the CPU is accessing memory (address bus carries memory address).
  • /WR — active-low write strobe; indicates the CPU is writing data to the bus.
  • /RD — active-low read strobe; indicates the CPU is reading data from the bus.
  • /RESET — system reset; held low during power-on reset and hardware reset conditions.
  • A0–A15 — 16-bit address bus driven by the CPU.
  • D0–D7 — 8-bit bidirectional data bus; driven by the CPU during writes and by the addressed device during reads.
  • GND — signal ground (pins 41 and 43).
  • CLOCK — 3.579545 MHz CPU clock output, derived from the NTSC colour sub-carrier oscillator.
  • SW1 / SW2 — cartridge insertion/removal detection pins; not connected in most implementations.
  • +5V — regulated +5 V supply (pins 45 and 47), maximum 300 mA per slot.
  • +12V — regulated +12 V supply (pin 48); shared 50 mA budget across all slots.
  • SOUNDIN — analogue audio input to the system mixer at −5 dBm nominal; used by FM-sound and wave-table sound cartridges.
  • −12V — regulated −12 V supply (pin 50); shared 50 mA budget across all slots.

References

Category:Cartridges - Expansions Connectors