The Nintendo Game Boy (DMG, 1989) uses a 32-pin edge connector, designated P1 on the main PCB, to interface with removable Game Pak cartridges. The connector carries a 16-bit address bus (A0–A15), an 8-bit bidirectional data bus (D0–D7), active-low control signals (/RESET, /RD, /WR, /CS), +5 V power supplied by an on-board DC-DC converter, and a VIN audio input line that routes external sound from the cartridge into the CPU mixer. The same physical 32-pin slot is shared by the Game Boy Pocket (MGB), Game Boy Light (MGL), and Game Boy Color (CGB), maintaining backward compatibility across all four systems. Game Paks may contain programme ROM, a Memory Bank Controller (MBC1, MBC2, MBC3, or MBC5), and optionally battery-backed SRAM for save data, a real-time clock (MBC3), or a rumble motor (MBC5 variant).
| Pin | Name | Description |
|---|---|---|
| 1 | VCC | +5 VDC |
| 2 | ? | ? Connected on Gameboy, but not used on GamePaks. |
| 3 | /RESET | Reset |
| 4 | /WR | Write |
| 5 | ? | ? Used by paging PAL on high capacity GamePaks. |
| 6 | A0 | Address 0 |
| 7 | A1 | Address 1 |
| 8 | A2 | Address 2 |
| 9 | A3 | Address 3 |
| 10 | A4 | Address 4 |
| 11 | A5 | Address 5 |
| 12 | A6 | Address 6 |
| 13 | A7 | Address 7 |
| 14 | A8 | Address 8 |
| 15 | A9 | Address 9 |
| 16 | A10 | Address 10 |
| 17 | A11 | Address 11 |
| 18 | A12 | Address 12 |
| 19 | A13 | Address 13 |
| 20 | A14 | Address 14 |
| 21 | /CS | Chip Select |
| 22 | D0 | Data 0 |
| 23 | D1 | Data 1 |
| 24 | D2 | Data 2 |
| 25 | D3 | Data 3 |
| 26 | D4 | Data 4 |
| 27 | D5 | Data 5 |
| 28 | D6 | Data 6 |
| 29 | D7 | Data 7 |
| 30 | /RD | Read |
| 31 | ? | ? Connected on Gameboy, but not used on Game-Paks. |
| 32 | GND | Ground |
Notes
The connector is a PCB edge connector; the Game Pak presents a gold-contact card edge that inserts into the 32-pin receptacle on the rear of the console. VCC on pin 1 is +5 V DC delivered by the console’s internal DC-DC converter from a battery input range of 3.5–7 V DC (four AA cells or equivalent rechargeable pack). The CPU IC is the Nintendo/Sharp LR35902, clocked at 4.194 MHz on DMG/MGB or switchable between 4.194 MHz and 8.389 MHz on CGB, giving a base instruction cycle of 0.954 µs. Battery-backed SRAM in the cartridge (used for save data) requires a cartridge battery voltage in the range 2.7–3.2 V DC. A separate 6-pin Game Link port on the console handles serial communication for multi-player and peripheral devices and is not part of the 32-pin cartridge interface.
Signals
- VCC — +5 V DC power supplied from the console to the cartridge via an on-board DC-DC converter.
- GND — Ground return.
- /RESET — Active-low reset signal; initialises cartridge logic on power-up or reset.
- /WR — Active-low write strobe; asserted by the CPU when writing to the cartridge data bus.
- /RD — Active-low read strobe; asserted by the CPU when reading from the cartridge.
- /CS — Active-low chip select; enables the cartridge ROM or RAM for a bus transaction.
- A0–A14 — 15-bit address bus lines driven by the CPU (part of the full 16-bit A0–A15 address space). Together they select the byte address within the currently active ROM or RAM bank.
- D0–D7 — 8-bit bidirectional data bus; transfers one byte per read or write cycle between the CPU and cartridge.
- Pin 2 — Function unknown; present on the console connector but not connected on standard Game Paks.
- Pin 5 — Function unknown; reportedly used for address routing in high-capacity Game Paks (consistent with MBC5 extended bank-switching), but its exact assignment is not defined in publicly available documentation.
- Pin 31 — Function unknown; present on the console connector but not connected on standard Game Paks.
- VIN — External audio input from the cartridge into the CPU’s sound mixer. Documented in the Nintendo Programming Manual as usable only in CGB mode; maximum input amplitude 3 V. Controlled via register NR50 bits 7 and 3.