The Commodore 128 expansion bus is a 44-pin (22 per side) female edge connector mounted on the rear panel of the machine, introduced in 1985 as part of the C128’s tri-mode architecture. It exposes the MOS 8502 CPU bus directly, with the upper eight address lines designated as “translated” (TA8–TA15) through the C128’s MMU to support its extended memory banking, whilst the lower eight (SA0–SA7) are shared with the C64-compatible address space. The connector is mechanically and electrically compatible with Commodore 64 cartridges, which operate correctly when the C128 is in C64 mode. The governing reference for pin assignments and electrical specifications is the Commodore 128 Programmer’s Reference Guide (Bantam Books / Commodore Business Machines, 1986), supplemented by the Commodore Service Manual PN-314001-08 (November 1987).
44 PIN FEMALE EDGE at the computer.
| Pin | Name | Description |
|---|---|---|
| 1 | GND | System Ground |
| 2 | +5V | System Vcc |
| 3 | +5V | System Vcc |
| 4 | /IRQ | Interrupt request |
| 5 | R/W | System Read/Write Signal |
| 6 | DClock | 8.18MHz Video Dot Clock |
| 7 | I/O1 | I/O Chip select $de00-deff |
| 8 | /GAME | Sensed for memory map configuration |
| 9 | /EXROM | Sensed for memory map configuration |
| 10 | I/O2 | I/O Chip select $df00-dfff |
| 11 | /ROML | External ROM select $8000-Bfff |
| 12 | BA | Bus available output |
| 13 | /DMA | Direct memory access input |
| 14 | D7 | Data bit 7 |
| 15 | D6 | Data bit 6 |
| 16 | D5 | Data bit 5 |
| 17 | D4 | Data bit 4 |
| 18 | D3 | Data bit 3 |
| 19 | D2 | Data bit 2 |
| 20 | D1 | Data bit 1 |
| 21 | D0 | Data bit 0 |
| 22 | GND | System Ground |
| A | GND | System Ground |
| B | /ROMH | External ROM Select $c000-ffff |
| C | /RESET | System Reset Signal |
| D | /NMI | Non-Maskable Interrupt |
| E | 1MHz | System 1MHz clock |
| F | TA15 | Translated address bit 15 |
| H | TA14 | Translated address bit 14 |
| J | TA13 | Translated address bit 13 |
| K | TA12 | Translated address bit 12 |
| L | TA11 | Translated address bit 11 |
| M | TA10 | Translated address bit 10 |
| N | TA9 | Translated address bit 9 |
| P | TA8 | Translated address bit 8 |
| R | SA7 | Shared address bit 7 |
| S | SA6 | Shared address bit 6 |
| T | SA5 | Shared address bit 5 |
| U | SA4 | Shared address bit 4 |
| V | SA3 | Shared address bit 3 |
| W | SA2 | Shared address bit 2 |
| X | SA1 | Shared address bit 1 |
| Y | SA0 | Shared address bit 0 |
| Z | GND | System Ground |
Notes
The connector uses 2.54 mm pitch and requires a male edge connector on the cartridge or expansion device. All bus lines are unbuffered direct connections to the CPU and must not exceed one LS TTL load per signal. The +5 V supply across pins 2 and 3 has a combined current limit shared with the rest of the system; expansion hardware should draw conservatively. Pin E carries the Phase 2 system clock (Φ2), labelled here as 1 MHz; its actual frequency tracks the system clock and varies slightly between NTSC and PAL variants. The /GAME and /EXROM lines are sensed at reset to determine the active memory map configuration. Asserting /DMA pulls the CPU address bus, data bus, and R/W line to high impedance, allowing an external device to take control of the bus. The connector is fully backward-compatible with Commodore 64 cartridges when the C128 is running in C64 mode; in native C128 mode the translated address lines (TA8–TA15) reflect MMU banking state and may differ from the physical address the CPU issued.
Signals
- GND — System ground; present on pins 1, 22, A, and Z.
- +5V — Regulated 5 V supply on pins 2 and 3; combined current budget shared with the system.
- /IRQ — Maskable interrupt request input to the CPU; active low.
- R/W — Read/write direction signal; high = read, low = write.
- DClock — 8.18 MHz video dot clock output derived from the system oscillator (NTSC figure).
- I/O1 — Active-low chip select for the I/O region $DE00–$DEFF.
- /GAME — Sensed at startup to select the cartridge memory map mode.
- /EXROM — Sensed at startup alongside /GAME to configure the ROM banking map.
- I/O2 — Active-low chip select for the I/O region $DF00–$DFFF.
- /ROML — Active-low ROM select for the low cartridge ROM window ($8000–$BFFF).
- BA — Bus Available; goes low three cycles before the VIC-II takes the system buses.
- /DMA — Direct Memory Access request input; asserting this tri-states the CPU bus.
- D7–D0 — Unbuffered eight-bit data bus.
- /ROMH — Active-low ROM select for the high cartridge ROM window ($C000–$FFFF).
- /RESET — System reset; active low.
- /NMI — Non-maskable interrupt request; active low.
- 1MHz — Phase 2 system clock output (Φ2); nominally ~1 MHz in C64 mode and C128 mode.
- TA15–TA8 — Upper eight translated address lines; reflect MMU-mapped addresses in C128 native mode.
- SA7–SA0 — Lower eight shared address lines; common to both C64 and C128 address spaces.