Commodore C16/+4 Expansion Bus

The Commodore C16, C116, and Plus/4 (the 264/TED family) share a 50-pin female edge connector with 2 mm pitch for cartridge and expansion devices — physically wider and finer-pitched than the 44-pin 2.54 mm connector used on the Commodore 64 and VIC-20, making the two families electrically and physically incompatible. The bus is built around the MOS 7501 CPU running at approximately 1 MHz and exposes the full 16-bit address bus (A0–A15), 8-bit data bus (D0–D7), and DRAM control signals including /RAS, /CAS, and MUX. Unique to the 264/TED family are the four cartridge chip-select lines C1LOW, C1HIGH, C2LOW, and C2HIGH, which directly select the internal ROM socket regions for external cartridge ROM. The C16 and C116 have no user port; only the Plus/4 adds one separately.

50 PIN FEMALE EDGE (2 mm pitch) at the Computer.

Notes

• The 50-pin 2 mm-pitch edge connector is physically incompatible with the Commodore 64’s 44-pin 2.54 mm expansion port; C64 cartridges cannot be used on C16/+4 hardware and vice versa.
• PHI2: address is valid on the rising edge; data is valid on the falling edge.
• PHI0 and PHI2 are the two non-overlapping clock phases derived from the TED chip; external devices should use PHI2 for data transfers.
• MUX is the DRAM address multiplex control signal: when asserted, the address bus carries the row address; when negated, it carries the column address.
• AEC (Address Enable Code) allows an external device to take control of the address bus; asserting it places the CPU address lines in a high-impedance state.
• C2LOW and C2HIGH are reserved cartridge chip-select lines; they are present on the connector but were not used by any Commodore-issued cartridge hardware.
• The C16 and C116 do not include a user port; the Plus/4 is the only 264-family machine to provide a separate user port connector.

Signals

• GND — Signal and power ground (pins 1, 25, A, CC)
• +5V — +5 VDC power supply to cartridge (pins 2, 3)
• /IRQ — Interrupt Request: active-low signal used by cartridges to interrupt the CPU
• R/W — Read/Write: high = CPU is reading, low = CPU is writing
• C1HIGH — Cartridge chip select C1 High: selects the upper bank of the C1 cartridge ROM region
• C1LOW — Cartridge chip select C1 Low: selects the lower bank of the C1 cartridge ROM region
• C2LOW — Cartridge chip select C2 Low: reserved; selects the lower bank of the C2 ROM region (not used by production cartridges)
• C2HIGH — Cartridge chip select C2 High: reserved; selects the upper bank of the C2 ROM region (not used by production cartridges)
• /CS1 — Chip Select 1: active-low select for the internal I/O region
• /CS0 — Chip Select 0: active-low select for the internal I/O region
• /CAS — Column Address Strobe: DRAM control signal indicating the address bus carries a column address
• MUX — DRAM address multiplex control: signals when the address bus is presenting a row versus column address
• BA — Bus Available: low indicates a DMA cycle is in progress
• D7–D0 — Data bus, bits 7 to 0 (bidirectional)
• AEC — Address Enable Code: when asserted, places CPU address lines in high-impedance state, allowing external DMA
• EAI — External Audio In: analogue audio input mixed with the TED chip’s internal sound output
• PHI2 — Phase 2 clock output from the TED chip; address valid on the rising edge, data valid on the falling edge
• /RAS — Row Address Strobe: DRAM control signal indicating the address bus carries a row address
• PHI0 — Phase 0 clock: complementary clock phase to PHI2, derived from the TED chip
• A15–A0 — Address bus, bits 15 to 0 (output from CPU)
• n/c — Not connected (pins Z, AA, BB)

References

• Service Manual Model C16 Computer (1984-10)(Commodore) [PN-314001-03]

Category:Cartridges - Expansions Connectors