The AY-3-8912 is a 28-pin DIP Programmable Sound Generator (PSG) by General Instrument, first incorporated in the ZX Spectrum 128 (1985) and retained in the +2, +2A, and +3 models. It generates sound via three independent tone channels (A, B, and C), one noise channel, an envelope generator, and one 8-bit parallel I/O port (IOA); the IOB port present on the related AY-3-8910 is absent in the 8912. The chip is clocked at 1.7734 MHz — half the 3.5469 MHz Z80 CPU clock — and operates from a single +5 V supply. On the ZX Spectrum 128, the Z80 selects a register by writing to I/O port 0xFFFD and transfers data via port 0xBFFD; BDIR and BC1 are decoded from address lines A14, A15, and /IORQ via discrete gates on the motherboard.
| Pin | Name | Description |
|---|---|---|
| 1 | SOUND C | Sound C (Can be tied together with A & B) |
| 2 | PORT | ? |
| 3 | VCC | +5 VDC |
| 4 | SOUND B | Sound B (Can be tied together with A & C) |
| 5 | SOUND A | Sound A (Can be tied together with B & C) |
| 6 | GND | Ground |
| 7 | PORT | ? |
| 8 | PORT | ? |
| 9 | PORT | ? |
| 10 | PORT | ? |
| 11 | PORT | ? |
| 12 | PORT | ? |
| 13 | PORT | ? |
| 14 | CLOCK | ? |
| 15 | CLOCK | ? |
| 16 | RESET | Reset |
| 17 | A8 | Address 8? |
| 18 | BDIR | ? |
| 19 | BC2 | ? |
| 20 | BC1 | ? |
| 21 | D7 | Data 7 |
| 22 | D6 | Data 6 |
| 23 | D5 | Data 5 |
| 24 | D4 | Data 4 |
| 25 | D3 | Data 3 |
| 26 | D2 | Data 2 |
| 27 | D1 | Data 1 |
| 28 | D0 | Data 0 |
Notes
The AY-3-8912 uses a 28-pin DIP package. Pins 7–14 (IOA0–IOA7) form the single I/O port; on the ZX Spectrum 128 these are connected to the RS-232/MIDI socket and the Keypad/Aux socket, and are not exposed on the main expansion connector. The bidirectional data/address bus (DA0–DA7, pins 21–28) carries both register addresses and data, multiplexed under control of BDIR and BC1. Each IOA pin has an on-chip pull-up resistor. The /RESET pulse must be held low for a minimum of 500 ns. Supply voltage is +5 V ±5 %; maximum supply current is 85 mA.
Signals
- SOUND A / SOUND B / SOUND C — analogue audio outputs for tone channels A, B, and C respectively; up to 1 V peak-to-peak per channel; may be summed together
- VCC — +5 V DC supply
- GND — ground reference
- PORT (pins 7–13) — IOA0–IOA6, bidirectional I/O port A lines; on ZX Spectrum 128 routed to RS-232/MIDI and Keypad sockets; each line has an on-chip pull-up resistor
- CLOCK (pin 14) — clock input; 1.7734 MHz on ZX Spectrum 128 (half the CPU clock); operating range 1–2 MHz; rise/fall time ≤50 ns
- CLOCK (pin 15) — IOA7, the eighth line of I/O port A; function as clock or I/O depends on package variant; purpose not publicly documented for this table entry
- RESET — active-low chip reset; minimum pulse width 500 ns
- A8 — high-order address input used with BC1/BC2/BDIR for chip-select decoding within a 1,024-word address space
- BDIR — bus direction control; combined with BC1 to select PSG operating mode (inactive, read, write, or latch address)
- BC2 — bus control 2; with BDIR and BC1 defines the bus transaction mode; on ZX Spectrum 128, decoded from A14, A15, and /IORQ
- BC1 — bus control 1; with BDIR selects: BDIR=0/BC1=1 read from PSG; BDIR=1/BC1=0 write to PSG; BDIR=1/BC1=1 latch register address
- D7–D0 — bidirectional 8-bit data/address bus (DA7–DA0); carries register address during latch cycle and read/write data during transfer cycles