The Commodore CDTV (CD1000, 1991) is an Amiga 500-based multimedia appliance that exposes an internal 80-pin diagnostic slot on the right side of its motherboard, designated CN12 in the CDTV Service Manual (PN 400403-01). The board-side connector is a KEL 8811 series 170L; the preferred mating connector for expansion cards is the KEL 8801-080-170S (alternatives: 8800-080-170S or 8802-080-170S). Pins 1–6 carry CDTV-specific power and AutoConfig signals, whilst pins 7–80 are electrically equivalent to pins 13–86 of the Amiga 500’s 86-pin side expansion connector (P2), presenting the full Motorola 68000 bus without buffering. Internal expansion cards connecting to this slot may provide up to 8 MB of 16-bit Fast RAM.
| Pin | Name | Description |
|---|---|---|
| 1 | GND | Ground |
| 2 | GND | Ground |
| 3 | VCC | +5 VDC |
| 4 | VCC | +5 VDC |
| 5 | /CFGOUT | Configout AutoConfig signal (not connected) |
| 6 | /CFGIN | Configin AutoConfig signal (grounded) |
| 7 | GND | Ground |
| 8 | CCKQ | 3.58 MHz CCKQ clock (C3) |
| 9 | CDAC | 7.16 MHz CDAC clock (90° before system clock) |
| 10 | CCK | 3.58 MHz CCK clock (C1) |
| 11 | /OVR | Override (Disables /DTACK generation of Gary) |
| 12 | XRDY | External Ready (Generates wait states while low). |
| 13 | /INT2 | Level 2 Interrupt |
| 14 | n/c | not connected |
| 15 | A5 | Address Bus 5 |
| 16 | /INT6 | Level 6 Interrupt |
| 17 | A6 | Address Bus 6 |
| 18 | A4 | Address Bus 4 |
| 19 | GND | Ground |
| 20 | A3 | Address Bus 3 |
| 21 | A2 | Address Bus 2 |
| 22 | A7 | Address Bus 7 |
| 23 | A1 | Address Bus 1 |
| 24 | A8 | Address Bus 8 |
| 25 | /FC0 | Processor Function Code Status (bit 0) |
| 26 | A9 | Address Bus 9 |
| 27 | /FC1 | Processor Function Code Status (bit 1) |
| 28 | A10 | Address Bus 10 |
| 29 | /FC2 | Processor Function Code Status (bit 2) |
| 30 | A11 | Address Bus 11 |
| 31 | GND | Ground |
| 32 | A12 | Address Bus 12 |
| 33 | A13 | Address Bus 13 |
| 34 | /IPL0 | Interrupt Priority Level (bit 0) |
| 35 | A14 | Address Bus 14 |
| 36 | /IPL1 | Interrupt Priority Level (bit 1) |
| 37 | A15 | Address Bus 15 |
| 38 | /IPL2 | Interrupt Priority Level (bit 2) |
| 39 | A16 | Address Bus 16 |
| 40 | /BERR | Bus Error |
| 41 | A17 | Address Bus 17 |
| 42 | /VPA | Valid Peripheral Address (asserted by Gary) |
| 43 | GND | Ground |
| 44 | E | E Clock |
| 45 | /VMA | Valid Memory Address (asserted by Gary) |
| 46 | A18 | Address Bus 18 |
| 47 | /RST | Reset |
| 48 | A19 | Address Bus 19 |
| 49 | /HLT | Halt |
| 50 | A20 | Address Bus 20 |
| 51 | A22 | Address Bus 22 |
| 52 | A21 | Address Bus 21 |
| 53 | A23 | Address Bus 23 |
| 54 | /BR | Bus Request |
| 55 | GND | Ground |
| 56 | /BGACK | Bus Grant Acknowledge |
| 57 | D15 | Data Bus 15 |
| 58 | /BG | Bus Grant |
| 59 | D14 | Data Bus 14 |
| 60 | /DTACK | Data Transfer Acknowledge (normally asserted by Gary) |
| 61 | D13 | Data Bus 13 |
| 62 | R/W | Read/Write (high=read, low=write) |
| 63 | D12 | Data Bus 12 |
| 64 | /LDS | Lower Data Strobe |
| 65 | D11 | Data Bus 11 |
| 66 | /UDS | Upper Data Strobe |
| 67 | GND | Ground |
| 68 | /AS | Address Strobe |
| 69 | D0 | Data Bus 0 |
| 70 | D10 | Data Bus 10 |
| 71 | D1 | Data Bus 1 |
| 72 | D9 | Data Bus 9 |
| 73 | D2 | Data Bus 2 |
| 74 | D8 | Data Bus 8 |
| 75 | D3 | Data Bus 3 |
| 76 | D7 | Data Bus 7 |
| 77 | D4 | Data Bus 4 |
| 78 | D6 | Data Bus 6 |
| 79 | GND | Ground |
| 80 | D5 | Data Bus 5 |
Notes
- Pins 7–80 are electrically equivalent to pins 13–86 of the Amiga 500’s 86-pin side expansion connector (P2); the signal definitions for those pins are documented in the Amiga Hardware Reference Manual (Commodore-Amiga, 3rd ed., 1991).
- Pins 1–6 differ from the A500 counterpart: they carry CDTV-specific VCC, GND, /CFGOUT, and /CFGIN lines.
- The board-side connector designator is CN12 per the CDTV Service Manual; the KEL 8811 series 170L is the motherboard-mounted part.
- /CFGIN (pin 6) is grounded; /CFGOUT (pin 5) is not connected on a bare slot.
- The 68000 CPU is connected directly to this slot without bus buffers, matching the unbuffered design of the Amiga 500 expansion port.
- The slot supports up to 8 MB of 16-bit Fast RAM via internal expansion cards.
- System clocks: CCKQ (pin 8, 3.58 MHz, C3 phase) and CCK (pin 10, 3.58 MHz, C1 phase); CDAC (pin 9) is a 7.16 MHz clock shifted 90° ahead of the system clock.
Signals
- GND — Signal ground (pins 1, 2, 7, 19, 31, 43, 55, 67, 79)
- VCC — +5 V supply (pins 3, 4)
- /CFGOUT — AutoConfig chain output; not connected on an empty slot (pin 5)
- /CFGIN — AutoConfig chain input; grounded on an empty slot (pin 6)
- CCKQ — 3.58 MHz colour clock, C3 phase (pin 8)
- CDAC — 7.16 MHz DRAM column-address clock, 90° ahead of system clock (pin 9)
- CCK — 3.58 MHz colour clock, C1 phase (pin 10)
- /OVR — Override; disables /DTACK generation by the Gary chip when asserted (pin 11)
- XRDY — External Ready; inserts wait states whilst held low (pin 12)
- /INT2 — Motorola 68000 level 2 interrupt (pin 13)
- n/c — Not connected (pin 14)
- A1–A23 — 68000 24-bit address bus (pins 15–53, interleaved with other signals)
- /INT6 — Motorola 68000 level 6 interrupt (pin 16)
- /FC0, /FC1, /FC2 — Motorola 68000 function code outputs indicating the current bus cycle type (pins 25, 27, 29)
- /IPL0, /IPL1, /IPL2 — Interrupt priority level inputs to the 68000 (pins 34, 36, 38)
- /BERR — Bus Error; signals an abnormal bus condition to the 68000 (pin 40)
- /VPA — Valid Peripheral Address; asserted by Gary to indicate a 6800-compatible cycle (pin 42)
- E — E clock; 68000 enable signal for synchronous peripheral access (pin 44)
- /VMA — Valid Memory Address; asserted by Gary in synchrony with E (pin 45)
- /RST — System reset (pin 47)
- /HLT — Halt; freezes the 68000 bus (pin 49)
- /BR — Bus Request; asserted by an expansion device to request bus mastership (pin 54)
- /BGACK — Bus Grant Acknowledge; confirms the expansion device has taken the bus (pin 56)
- /BG — Bus Grant; issued by the 68000 in response to /BR (pin 58)
- /DTACK — Data Transfer Acknowledge; normally asserted by Gary (pin 60)
- R/W — Read/Write direction; high = read, low = write (pin 62)
- /LDS — Lower Data Strobe; qualifies the low byte (D0–D7) of the data bus (pin 64)
- /UDS — Upper Data Strobe; qualifies the high byte (D8–D15) of the data bus (pin 66)
- /AS — Address Strobe; indicates a valid address on the bus (pin 68)
- D0–D15 — 68000 16-bit data bus (pins 57–80, interleaved with other signals)