The Atari 7800 ProSystem (released in the USA in 1984 and again at retail in 1986) uses a 32-pin edge connector for its cartridge slot. The connector is a strict superset of the Atari 2600/VCS cartridge connector: pins 3–14 and 19–30 replicate the 2600 pinout exactly, enabling unmodified 2600 cartridges to run in compatibility mode. The remaining pins extend the address bus to a full 16 lines (A0–A15), add the R/W and CLK2 (phase-2 clock) control signals, and introduce HALT and IRQ lines used by the MARIA graphics chip and the 6502C (Sally) CPU. The cartridge bus is a passive, bus-mapped parallel interface with no serial protocol; the CPU drives the address and control lines directly and the cartridge ROM returns data on D0–D7.
| Pin | Name | Description |
|---|---|---|
| 1 | R/W | Read/Write |
| 2 | HALT | Halt |
| 3 | D3 | Data 3 |
| 4 | D4 | Data 4 |
| 5 | D5 | Data 5 |
| 6 | D6 | Data 6 |
| 7 | D7 | Data 7 |
| 8 | A12 | Address 12 |
| 9 | A10 | Address 10 |
| 10 | A11 | Address 11 |
| 11 | A9 | Address 9 |
| 12 | A8 | Address 8 |
| 13 | +5V | +5 VDC |
| 14 | GND | Ground |
| 15 | A13 | Address 13 |
| 16 | A14 | Address 14 |
| 17 | A15 | Address 15 |
| 18 | EAUDIO | EAudio ??? |
| 19 | A7 | Address 7 |
| 20 | A6 | Address 6 |
| 21 | A5 | Address 5 |
| 22 | A4 | Address 4 |
| 23 | A3 | Address 3 |
| 24 | A2 | Address 2 |
| 25 | A1 | Address 1 |
| 26 | A0 | Address 0 |
| 27 | D0 | Data 0 |
| 28 | D1 | Data 1 |
| 29 | D2 | Data 2 |
| 30 | Gnd | Gnd |
| 31 | IRQ | Interrupt |
| 32 | CLK2 | Clock 2 ??? |
Notes
The connector is an edge connector on the cartridge PCB itself; the console housing guides the cartridge into alignment. Pins 3–14 and 19–30 are electrically identical to the Atari 2600 cartridge connector, which is why the 7800 can run 2600 software without additional hardware. All signal lines operate at TTL/CMOS-compatible levels (VOH ≥ 2.4 V, VOL ≤ 0.4 V); the supply voltage for cartridge logic is +5 V (pin 13). The 1984 NTSC motherboard schematic designates the cartridge connector as J1; J3 and J4 are the controller ports. The motherboard supports ROM packages of 26-pin, 24-pin, and 28-pin (256 Kbit) configurations as documented in that schematic.
Signals
- R/W — read/write control from the 6502C (Sally) CPU; high = read, low = write.
- HALT — asserted by the MARIA graphics chip to suspend the CPU during DMA display-list processing.
- D3–D7 — upper five lines of the 8-bit bidirectional data bus; shared with the 2600-compatible subset.
- A12, A10, A11, A9, A8 — address lines; note the non-sequential ordering on these pins matches the 2600 connector layout retained for compatibility.
- +5V — +5 VDC supply for cartridge logic (pin 13).
- GND — ground return (pins 14 and 30).
- A13, A14, A15 — upper address lines extending the bus to 16 bits (64 KB address space); not present on the 2600 connector.
- EAUDIO — cartridge audio input mixed into the console’s audio output; function not detailed in the developer guide beyond signal name.
- A7–A0 — lower eight address lines; present on both 2600-compatible and 7800-specific cartridges.
- D0–D2 — lower three lines of the 8-bit bidirectional data bus; shared with the 2600-compatible subset.
- IRQ — interrupt request line to the 6502C CPU.
- CLK2 — phase-2 clock output from the console, supplied to the cartridge for timing purposes; function marked uncertain on some early documentation.