Commodore C64 Cartridge

44-pin female edge connector on the rear of the Commodore 64 providing direct access to the unbuffered CPU address and data buses for cartridges and expansion hardware.

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The Commodore 64 cartridge port is a 44-pin (22 per side) female edge connector mounted on the rear of the C64, introduced with the machine in 1982. It exposes the unbuffered MOS 6510 CPU address bus (A0–A15) and data bus (D0–D7) directly to the expansion slot, along with control lines for memory mapping, interrupts, and DMA. Cartridges and expansion hardware plug in via a male edge connector and must respect a combined +5 V current limit of 450 mA and a maximum of one LS TTL load per signal. The /GAME and /EXROM lines configure the C64 memory map to enable ROM banking, while /DMA places the CPU address, data, and R/W lines into high-impedance state to allow direct memory access by expansion hardware.

44 PIN FEMALE EDGE at the computer.

Commodore C64 Cartridge connector diagram

PinNameDescription
1GNDGround
2+5V+5 Volts DC
3+5V+5 Volts DC
4/IRQInterrupt Request
5R/W
6DOTCLKDot Clock
7I/O 1
8/GAMEGame
9/EXROM
10I/O 2
11/ROMLROM Low
12BA
13/DMA
14CD7Cartridge Data 7
15CD6Cartridge Data 6
16CD5Cartridge Data 5
17CD4Cartridge Data 4
18CD3Cartridge Data 3
19CD2Cartridge Data 2
20CD1Cartridge Data 1
21CD0Cartridge Data 0
22GNDGround
AGNDGround
B/ROMHROM High
C/RESETReset
D/NMINon Maskable Interrupt
EPHI2
FCA15Cartridge Address 15
HCA14Cartridge Address 14
JCA13Cartridge Address 13
KCA12Cartridge Address 12
LCA11Cartridge Address 11
MCA10Cartridge Address 10
NCA9Cartridge Address 9
PCA8Cartridge Address 8
RCA7Cartridge Address 7
SCA6Cartridge Address 6
TCA5Cartridge Address 5
UCA4Cartridge Address 4
VCA3Cartridge Address 3
WCA2Cartridge Address 2
XCA1Cartridge Address 1
YCA0Cartridge Address 0
ZGNDGround

Notes

The connector is a 44-pin (22 per side) female edge connector with 2.54 mm pitch. Male edge connectors on cartridges and peripherals insert from the rear. Pins 1, 22, A, and Z are ground; pins 2 and 3 supply +5 V DC with a combined current limit of 450 mA for all expansion devices. All address and data lines are unbuffered and must not be driven by more than one LS TTL load. The /GAME and /EXROM lines are sampled at power-on and during operation to select one of several memory-map configurations; pulling both low maps an 8 kB ROM at $8000–$9FFF (/ROML) and a further 8 kB at $A000–$BFFF (/ROMH). Asserting /DMA forces the CPU address bus, data bus, and R/W line to high-impedance, granting the expansion device direct bus access. The Bus Available (BA) signal goes low approximately three clock cycles before the VIC-II video chip takes control of the system buses.

Signals

  • GND — Signal and power ground (pins 1, 22, A, Z)
  • +5V — +5 V DC supply; combined limit 450 mA across both pins (pins 2, 3)
  • /IRQ — Maskable interrupt request; active low, open-collector
  • R/W — CPU read/write; high = read, low = write (write active low)
  • DOTCLK — Video dot clock; 8.181816 MHz (NTSC) or 7.881984 MHz (PAL)
  • I/O 1 — I/O select 1; active low, decodes addresses $DE00–$DEFF
  • /GAME — Game line; pulled low by cartridge to enable ROM banking modes
  • /EXROM — External ROM; pulled low by cartridge to map ROM into address space
  • I/O 2 — I/O select 2; active low, decodes addresses $DF00–$DFFF
  • /ROML — ROM Low select; active low, enables 8 kB at $8000–$9FFF
  • BA — Bus Available; goes low ~3 cycles before VIC-II takes the system buses
  • /DMA — Direct Memory Access request; asserted low places CPU bus in high-impedance state
  • CD7–CD0 — Cartridge data bus bits 7–0; unbuffered, 1 LS TTL load maximum
  • /ROMH — ROM High select; active low, enables 8 kB at $A000–$BFFF or $E000–$FFFF
  • /RESET — System reset; active low
  • /NMI — Non-maskable interrupt; active low, open-collector
  • PHI2 — Phase 2 system clock (~1 MHz); CPU clock output used for bus timing
  • CA15–CA0 — Cartridge address bus bits 15–0; unbuffered, 1 LS TTL load maximum

References

Category:Cartridges - Expansions Connectors