The Super Nintendo Entertainment System (SNES) uses a proprietary 62-pad edge connector to interface game cartridges with the console, introduced with the system’s launch in 1990 (Japan) and 1991 (North America and Europe). The connector carries a 24-bit CPU address bus (A0–A23), an 8-bit data bus (D0–D7), an 8-bit peripheral B-bus (PA0–PA7), power rails at +5 V, and dedicated pins for the CIC lockout chip. Pins operate at 5 V TTL/CMOS logic levels and the system clock runs at 21.47727 MHz (NTSC). Enhancement chips such as the SA-1, Super FX, and DSP-1 use additional expansion pads on the connector that standard mask-ROM cartridges leave unconnected.
| Pin | Name | Description |
|---|---|---|
| 1 | ||
| 2 | ||
| 3 | ||
| 4 | ||
| 5 | GND | Ground |
| 6 | A11 | Address 11 |
| 7 | A10 | Address 10 |
| 8 | A9 | Address 9 |
| 9 | A8 | Address 8 |
| 10 | A7 | Address 7 |
| 11 | A6 | Address 6 |
| 12 | A5 | Address 5 |
| 13 | A4 | Address 4 |
| 14 | A3 | Address 3 |
| 15 | A2 | Address 2 |
| 16 | A1 | Address 1 |
| 17 | A0 | Address 0 |
| 18 | /IRQ | Interrupt |
| 19 | D0 | Data 0 |
| 20 | D1 | Data 1 |
| 21 | D2 | Data 2 |
| 22 | D3 | Data 3 |
| 23 | /READ | Read |
| 24 | CIC | ? |
| 25 | CIC | ? |
| 26 | /RAM ENABLE | RAM Enable |
| 27 | VCC | +5 VDC |
| 28 | ||
| 29 | ||
| 30 | ||
| 31 | ||
| 32 | ||
| 33 | ||
| 34 | ||
| 35 | ||
| 36 | GND | Ground |
| 37 | A12 | Address 12 |
| 38 | A13 | Address 13 |
| 39 | A14 | Address 14 |
| 40 | A15 | Address 15 |
| 41 | A16 | Address 16 |
| 42 | A17 | Address 17 |
| 43 | A18 | Address 18 |
| 44 | A19 | Address 19 |
| 45 | A20 | Address 20 |
| 46 | A21 | Address 21 |
| 47 | A22 | Address 22 |
| 48 | A23 | Address 23 |
| 49 | /ROM ENABLE | ROM Enable |
| 50 | D4 | Data 4 |
| 51 | D5 | Data 5 |
| 52 | D6 | Data 6 |
| 53 | D7 | Data 7 |
| 54 | /WRITE | Write |
| 55 | CIC | ? |
| 56 | CIC | ? |
| 57 | n/c | Not connected |
| 58 | VCC | +5 VDC |
| 59 | ||
| 60 | ||
| 61 | ||
| 62 |
Notes
The connector is a 62-pad edge connector with 2.5 mm pad pitch, carrying 31 pads on the front side (pins 1–31) and 31 on the back (pins 32–62). Pins 1–4, 28–31 (front) and 32–35, 59–62 (back) are enhancement-chip expansion pads; standard mask-ROM cartridges leave these unconnected. CIC lockout chip signals occupy pins 24, 25, 55, and 56 on standard cartridges. The SYSTEM CLK (21.47727 MHz NTSC) is present on pin 1; PHI2 (the CPU-derived clock) appears on pin 57, which is unused by standard ROM cartridges.
Signals
- A0–A23 — 24-bit CPU A-bus address lines; A0–A11 on pins 6–17, A12–A23 on pins 37–48
- D0–D7 — 8-bit bidirectional data bus; D0–D3 on pins 19–22, D4–D7 on pins 50–53
- /IRQ — Interrupt request line to the CPU (active low), pin 18
- /READ — Read strobe from the CPU (active low), pin 23
- /WRITE — Write strobe from the CPU (active low), pin 54
- /ROM ENABLE — ROM chip-select (active low), pin 49; asserted when the CPU addresses the cartridge ROM area
- /RAM ENABLE — Work-RAM select (active low), pin 26; used for cartridge battery-backed SRAM
- CIC — Copy-protection lockout chip interface pins (pins 24, 25, 55, 56); function details are not publicly documented by Nintendo
- VCC — +5 V supply, pins 27 and 58
- GND — Ground, pins 5 and 36
References
- SNES Development Manual (Book I & Book II) — Nintendo of America, 1993