PCI Express 1x - 64 pin
Female Connector
PCI Express was introduced to overcome the limitations of the original PCI bus. Developed and released by Intel over a decade ago, the original PCI bus operated at 33MHz and 32 bits with a peak theoretical bandwidth of 132MB per second. It used a shared bus topology – bus bandwidth is shared among multiple devices - to enable communication among the different devices on the bus.
| Pin | Side B Connector | Side A Connector |
|---|---|---|
| # | Name | Description |
| 1 | +12v | +12 volt power |
| 2 | +12v | +12 volt power |
| 3 | RSVD | Reserved |
| 4 | GND | Ground |
| 5 | SMCLK | SMBus clock |
| 6 | SMDAT | SMBus data |
| 7 | GND | Ground |
| 8 | +3.3v | +3.3 volt power |
| 9 | JTAG1 | +TRST# |
| 10 | 3.3Vaux | 3.3v volt power |
| 11 | WAKE# | Link Reactivation |
| 12 | RSVD | Reserved |
| 13 | GND | Ground |
| 14 | HSOp(0) | Transmitter Lane 0, Differential pair |
| 15 | HSOn(0) | GND |
| 16 | GND | Ground |
| 17 | PRSNT#2 | Hotplug detect |
| 18 | GND | Ground |
| 19 | HSOp(1) | Transmitter Lane 1, Differential pair |
| 20 | HSOn(1) | GND |
| 21 | GND | Ground |
| 22 | GND | Ground |
| 23 | HSOp(2) | Transmitter Lane 2, Differential pair |
| 24 | HSOn(2) | GND |
| 25 | GND | Ground |
| 26 | GND | Ground |
| 27 | HSOp(3) | Transmitter Lane 3, Differential pair |
| 28 | HSOn(0) | GND |
| 29 | GND | Ground |
| 30 | RSVD | Reserved |
| 31 | PRSNT#2 | Hot plug detect |
| 32 | GND | Ground |
References
- Intel® Developer Network for PCI Express Architecture (contains a lot of technical documents)
- Ineerfacebus.com: PCI Express Bus Description
- National Instruments: Introduction to PCI Express