connector wiring scheme
| Pin | Name | Direction | Description |
|---|---|---|---|
| 1 | TCK | OUT | Test Clock |
| 2 | GND | - | Ground |
| 3 | TDI | OUT | Test Data Input |
| 4 | GND | - | Ground |
| 5 | TDO | IN | Test Data Output |
| 6 | VCC | - | Power Supply |
| 7 | TMS | OUT | Test Mode Select |
| 8 | TRS | OUT | Test Reset |
JTAG Header for FPGA/CPLD Applications (Comcom Electronics Standard)
